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Patent # Description
US-9,960,083 Method for fabricating semiconductor device
First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is...
US-9,960,082 Stack type semiconductor memory device
A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of...
US-9,960,081 Method for selective etching using dry film photoresist
A method for selective etching using a dry film photoresist includes forming an opening through a substrate from a first surface to expose a stop layer at a...
US-9,960,080 Method for bonding and interconnecting integrated circuit devices
A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded...
US-9,960,079 Passive within via
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also...
US-9,960,078 Reflow interconnect using Ru
A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and...
US-9,960,077 Ultra-scale gate cut pillar with overlay immunity and method for producing the same
Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments...
US-9,960,076 Devices with backside metal structures and methods of formation thereof
A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate...
US-9,960,075 Method of manufacturing semiconductor integrated circuit device
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain...
US-9,960,074 Integrated bi-layer STI deposition
A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into...
US-9,960,073 Substrate processing apparatus and substrate processing method
Disclosed is a substrate processing apparatus and method which facilitate to improve uniformity of thin film material and also facilitate to control quality of...
US-9,960,072 Variable adjustment for precise matching of multiple chamber cavity housings
A vertical adjustment assembly is disclosed in order to provide for matching vertical positions of two substrates within separate chambers or cavities of a...
US-9,960,071 Polishing apparatus and semiconductor manufacturing method
A polishing apparatus according to an embodiment includes a first polishing part, a second polishing part, and an annular part. The second polishing part...
US-9,960,070 Chucking warped wafer with bellows
A vacuum chuck has at least one suction assembly that pulls a wafer surface toward a chucking surface. The suction assembly may be used with a wafer that is...
US-9,960,069 Joining device and joining system
A joining device for joining substrates together includes a first holding member configured to vacuum-suck a first substrate to draw and hold the first...
US-9,960,068 Moment cancelling pad raising mechanism in wafer positioning pedestal for semiconductor processing
An assembly used in a process chamber for depositing a film on a wafer including a pedestal assembly having a pedestal movably mounted to a main frame. A lift...
US-9,960,067 Electrostatic chuck
According to an aspect of an embodiment of the invention, there is provided an electrostatic chuck including: a ceramic dielectric substrate including a first...
US-9,960,065 Substrate processing apparatus for managing transfer state of substrate gas storage container based on supply...
Provided are a substrate processing apparatus, a method of manufacturing a semiconductor device, and a non-transitory computer-readable recording medium, which...
US-9,960,064 Substrate storing container
The lateral substrate support part has: a plurality of plate parts, which have a parallel positional relationship, and support end portions of a plurality of...
US-9,960,063 Substrate transport apparatus and substrate transport method
An apparatus for transporting a substrate includes a base, a holding device which retracts relative to the base and holds multiple substrates in multiple...
US-9,960,062 Effluent control system
An apparatus, method, and system for collecting data related to effluent emitted from tools in semiconductor fabrication facilities using one or more sensors to...
US-9,960,061 Method and device for curing at least in part a photoresist applied to a substrate
A method for curing at least in part a photoresist applied to a substrate comprises the following steps: The substrate coated with the photoresist is arranged...
US-9,960,060 Platen assembly
A platen assembly includes a base and a clamping layer fixed to the base. A portion of the base that faces the clamping layer and a portion of the clamping...
US-9,960,059 Honeycomb heaters for integrated circuit manufacturing
A honeycomb heater includes a lamp housing having an outer edge that forms a partial circle. The lamp housing has an opening extending from a top surface to a...
US-9,960,058 Device and method for treating substrate surfaces
A device and method for treatment of a substrate treatment surface of a substrate with a fluid by immersion of the substrate treatment surface into the fluid....
US-9,960,057 Device for measuring the distribution or impulse of a series of droplets
A device for measuring the distribution and/or impulse of a series of droplets comprises a piezoelectric sensor positioned relative to a source of droplets such...
US-9,960,056 Substrate cleaning method, substrate cleaning apparatus and vacuum processing system
In order to remove a deposit adhered to the backside of the peripheral portion of a wafer, a cleaning gas containing carbon dioxide gas is set to a pressure...
US-9,960,055 Manufacturing method of semiconductor device
In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower...
US-9,960,054 Encapsulated dies with enhanced thermal performance
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip...
US-9,960,053 FinFET doping methods and structures thereof
A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack...
US-9,960,052 Methods for etching a metal layer to form an interconnection structure for semiconductor applications
Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor...
US-9,960,051 Activation method for silicon substrates comprising at least two aromatic acids
The present invention relates to an activation composition for activation of silicon substrates, which is an aqueous solution comprising a source of palladium...
US-9,960,050 Hard mask removal method
A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask...
US-9,960,049 Two-step fluorine radical etch of hafnium oxide
In one implementation, a method of removing a metal-containing layer is provided. The method comprises generating a plasma from a fluorine-containing gas. The...
US-9,960,048 Surface machining method for single crystal SiC substrate, manufacturing method thereof, and grinding plate for...
A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad...
US-9,960,047 Test pattern for trench poly over-etched step and formation method thereof
A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a...
US-9,960,046 Methods of manufacturing semiconductor device having a blocking insulation layer
A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of...
US-9,960,045 Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure
In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap "island." As a result, the charge-trap region of one memory...
US-9,960,044 Semiconductor device and methods for forming a semiconductor device
A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion...
US-9,960,043 Process of forming semiconductor device
A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a...
US-9,960,042 Carbon dopant gas and co-flow for implant beam and source life performance improvement
Ion implantation processes and systems are described, in which carbon dopant source materials are utilized to effect carbon doping. Various gas mixtures are...
US-9,960,041 Deposition apparatus
A deposition apparatus including a crucible to receive the deposition material and in which a deposition material is evaporated; a linear deposition source...
US-9,960,040 Manufacturing method of silicon carbide semiconductor device
In producing a MOS silicon carbide semiconductor device, after a first heat treatment (oxynitride) is performed in an oxidation atmosphere including nitrous...
US-9,960,039 Method of forming pattern and method of manufacturing integrated circuit device by using the same
A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality...
US-9,960,038 Processes to pattern small features for advanced patterning needs
Methods of forming microelectronic structure are provided. The methods comprise the formation of T-shaped structures using a controlled undercutting process,...
US-9,960,037 Laser assisted SiC growth on silicon
A method for forming a compound on a substrate is provided. The method includes depositing a composition onto a surface of a substrate; illuminating the...
US-9,960,036 Method and apparatus for forming device quality gallium nitride layers on silicon substrates
Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400.degree. C. The substrate and film materials...
US-9,960,035 Variable frequency microwave (VFM) processes and applications in semiconductor thin film fabrications
Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating...
US-9,960,034 Method of forming a thin film that eliminates air bubbles
A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor...
US-9,960,033 Method of depositing and etching Si-containing film
A method of filling recesses or grooves on a patterned surface with a layer of film, by combining depositing a film by PEALD/PPECVD on the patterned surface and...
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