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Patent # Description
US-9,966,342 Black marker composition and an electronic component using these
The object of the present invention is to provide a black marker composition capable of forming non-metal marker which sufficiently ensures the adhering...
US-9,966,341 Input/output pins for chip-embedded substrate
Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed...
US-9,966,340 Flexible substrate for packaging and package
The present invention provides a flexible substrate for packaging and a package. The flexible substrate for packaging includes a bendable region provided in a...
US-9,966,339 Barrier structure for copper interconnect
A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a...
US-9,966,338 Pre-spacer self-aligned cut formation
Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is...
US-9,966,337 Fully aligned via with integrated air gaps
A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the...
US-9,966,336 Hybrid interconnect scheme and methods for forming the same
A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k...
US-9,966,335 Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The...
US-9,966,334 Semiconductor module
A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad...
US-9,966,333 Semiconductor substrate, semiconductor module and method for manufacturing the same
A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second...
US-9,966,332 Solid-state device including a conductive bump connected to a metal pattern and method of manufacturing the same
A solid-state device includes a metal pattern formed on a substrate, a conductive bump connected to the metal pattern so as to be contact with a side surface of...
US-9,966,331 Wiring substrate and semiconductor device
The wiring substrate includes an insulation layer that includes a lower surface, an upper surface, and an intermediate surface located between the lower surface...
US-9,966,330 Stack die package
In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first...
US-9,966,329 Method for manufacturing semiconductor device
Reliability of a semiconductor device is improved. A method for manufacturing the semiconductor device includes the steps of: providing a lead frame having a...
US-9,966,328 Semiconductor power device having single in-line lead module and method of making the same
A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or...
US-9,966,327 Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing...
A lead frame according to one embodiment includes a lead part including an inner lead and an outer lead connected to the inner lead, and a frame unit supporting...
US-9,966,326 Lead frames with wettable flanks
A method of producing wettable fillets in electronic packages. A matrix of unsingulated lead frames is provided, each including a plurality of lead elements and...
US-9,966,325 Semiconductor die package and method of producing the package
A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in...
US-9,966,324 Thermally conductive sheet, method for producing same, and semiconductor device
A thermally conductive sheet, which contains: a binder; carbon fibers; and an inorganic filler, wherein the thermally conductive sheet is to be sandwiched...
US-9,966,323 Semiconductor device
A semiconductor device includes an electronic component connected to a component pad of a wiring substrate, a connection member connected to a connection pad of...
US-9,966,322 Semiconductor device
A semiconductor device includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer has...
US-9,966,321 Methods and apparatus for package with interposers
An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size...
US-9,966,320 Wafer level package solder barrier used as vacuum getter
An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the...
US-9,966,319 Environmental hardening integrated circuit method and apparatus
A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended...
US-9,966,318 System for electrical testing of through silicon vias (TSVs)
A substrate includes first and second semiconductor layers doped with opposite conductivity type in contact with each other at a PN junction to form a junction...
US-9,966,317 Semiconductor device and semiconductor package comprising the same
A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second...
US-9,966,316 Deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device
According to one embodiment, deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device includes a depositing...
US-9,966,315 Advanced process control methods for process-aware dimension targeting
Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed...
US-9,966,313 FinFET device and method of manufacturing
A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments...
US-9,966,312 Method for etching a silicon-containing substrate
Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include...
US-9,966,311 Semiconductor device manufacturing method
A semiconductor device manufacturing method according to an embodiment including partially forming a first groove on a nitride semiconductor layer provided on a...
US-9,966,310 Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side...
US-9,966,309 Contact plug without seam hole and methods of forming the same
A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the...
US-9,966,308 Semiconductor device and method of forming the semiconductor device
A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric...
US-9,966,307 Method and system for uniform deposition of metal
A method for manufacturing a semiconductor device includes providing a substrate, performing a nucleation process on the substrate to form a nucleation layer of...
US-9,966,306 Catalyst layer forming method, catalyst layer forming system and recording medium
A catalyst adsorbed on a surface of a substrate is bound to the substrate without leaving residues within a recess of the substrate. A catalyst layer forming...
US-9,966,305 Ion flow barrier structure for interconnect metallization
A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first...
US-9,966,304 Method for forming interconnect structure
An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower...
US-9,966,303 Microelectronic elements with post-assembly planarization
A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at...
US-9,966,302 Device manufacture and packaging method thereof
Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive...
US-9,966,301 Reduced substrate effects in monolithically integrated RF circuits
A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle...
US-9,966,300 Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of...
US-9,966,299 Inhibitor plasma mediated atomic layer deposition for seamless feature fill
Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber...
US-9,966,298 Multiple-stage processing devices
A multiple stage processing device having a plurality of radial stages, each individual radial stage is positioned between adjacent dividing walls and indexable...
US-9,966,297 Semiconductor wafer protective film and method of manufacturing semiconductor device
According to the present invention, there is provided a semiconductor wafer protective film including a substrate layer (A) and an adhesive layer (C) formed on...
US-9,966,296 Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the...
The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same...
US-9,966,295 Temporary bonding laminates for use in manufacture of semiconductor devices and method for manufacturing...
A temporary bonding laminate for use in the manufacture of semiconductor devices and a method for manufacturing semiconductor devices are provided. A member to...
US-9,966,294 Mobile electrostatic carrier for a semiconductive wafer and a method of using thereof for singulation of the...
A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive...
US-9,966,293 Wafer arrangement and method for processing a wafer
A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are...
US-9,966,292 Centering fixture for electrostatic chuck system
A centering fixture for centering a wafer on a chuck is provided. The centering fixture includes a body including an upper surface, a lower surface, an inner...
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