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Patent # Description
US-9,972,647 Display device having pixel including transistors
A first capacitor obtains a gate-source voltage of a first transistor in accordance with a programming current flowing through the first transistor, and a...
US-9,972,646 Semiconductor device and manufacturing method of the same
An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source...
US-9,972,645 Flexible display device
A flexible display device including a substrate having an active region in which an input image is implemented and a bezel region outside the active region; a...
US-9,972,644 Semiconductor device and method for forming the same
The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide...
US-9,972,643 Array substrate and fabrication method thereof, and display device
An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a thin film transistor (TFT 10) provided...
US-9,972,642 High voltage three-dimensional devices having dielectric liners
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are...
US-9,972,641 Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory...
US-9,972,640 Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack...
US-9,972,639 Semiconductor device comprising a conductive layer having an air gap
A semiconductor device includes a substrate, gate electrodes and interlayer insulating layers alternately stacked on the substrate, channel regions penetrating...
US-9,972,638 Methods of fabricating three-dimensional semiconductor devices
Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating...
US-9,972,637 Metal-ono-vacuum tube charge trap flash (VTCTF) nonvolatile memory and the method for making the same
The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using ...
US-9,972,636 Vertical memory devices having dummy channel regions
A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate...
US-9,972,635 Semiconductor memory device and method for manufacturing same
A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second...
US-9,972,634 Semiconductor device comprising a floating gate flash memory device
A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk...
US-9,972,633 Semiconductor device and method for fabricating the same
A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a...
US-9,972,632 Split-gate, twin-bit non-volatile memory cell
A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and...
US-9,972,631 Memory device and method of manufacturing the same
Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate...
US-9,972,630 Split gate non-volatile flash memory cell having metal gates and method of making same
A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area....
US-9,972,629 Semiconductor integrated circuit device
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential...
US-9,972,628 Conductive structures, wordlines and transistors
Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive...
US-9,972,627 Semiconductor device having passing gate and method for fabricating the same
A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain...
US-9,972,626 Dynamic random access memory and method of fabricating the same
Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged...
US-9,972,625 Method of manufacturing semiconductor integrated circuit device
Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high...
US-9,972,624 Layout construction for addressing electromigration
A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first...
US-9,972,623 Semiconductor device including barrier layer and manufacturing method thereof
A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a...
US-9,972,622 Method for manufacturing a CMOS device and associated device
A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer,...
US-9,972,621 Fin structure in sublitho dimension for high performance CMOS application
A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI...
US-9,972,620 Preventing shorting between source and/or drain contacts and gate
Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and...
US-9,972,619 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor...
Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a...
US-9,972,618 Semiconductor device
An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type...
US-9,972,617 Power semiconductor device having trench gate type IGBT and diode regions
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
US-9,972,616 Methods of forming tuneable temperature coefficient FR embedded resistors
Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an...
US-9,972,615 Semiconductor device for electrostatic discharge protection
A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is...
US-9,972,614 Overheat detection circuit and power supply apparatus
Provided is an overheat detection circuit having a small circuit scale, low cost, and low electric power consumption. The overheat detection circuit implemented...
US-9,972,613 Semiconductor device including a phase change material
A semiconductor device includes a transistor having a plurality of transistor cells in a semiconductor body. Each transistor cell includes a control terminal...
US-9,972,612 Semiconductor device
A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main...
US-9,972,611 Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package
A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory...
US-9,972,610 System-in-package logic and method to control an external packaged memory device
Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a...
US-9,972,609 Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor
Package-on-package ("PoP") devices with WLP ("WLP") components with dual RDLs ("RDLs") for surface mount dies and methods therefor. In a PoP, a first IC die...
US-9,972,608 Light emitting diode device
A light emitting diode device is provided. The light emitting diode device has a substrate, a plurality of metal pads, a plurality of LEDs and a first metal...
US-9,972,607 Semiconductor device and method of integrating power module with interposer and opposing substrates
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the...
US-9,972,606 Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a...
US-9,972,605 Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby
A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first...
US-9,972,604 Joint structure for metal pillars
A female structure embedding a first metal pillar and a male structure embedding a second metal pillar. The female structure and the male structure can be...
US-9,972,603 Seal-ring structure for stacking integrated circuits
A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first...
US-9,972,602 Method and apparatus for interconnecting stacked dies using metal posts
Embodiments include a semiconductor package comprising a first die having (i) a first side and (ii) a second side, wherein the first die comprises a first...
US-9,972,601 Integrated circuit package having wirebonded multi-die stack
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
US-9,972,600 Semiconductor device including protective film over a substrate
A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective...
US-9,972,599 Package structure and method of manufacturing the same
A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming up plurality of first conductors...
US-9,972,598 Method of manufacturing semiconductor device
Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere,...
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