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Patent # Description
US-9,972,597 Method of bonding with silver paste
A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of...
US-9,972,596 Chip assemblage, press pack cell and method for operating a press pack cell
One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an...
US-9,972,595 Bonding wire for high-speed signal line
A bonding wire for a high-speed signal line for connecting a pad electrode of a semiconductor device and a lead electrode on a circuit board contains palladium...
US-9,972,593 Semiconductor package
The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface...
US-9,972,592 Bumped land grid array
A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a...
US-9,972,591 Method of manufacturing semiconductor device
To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in...
US-9,972,590 Semiconductor package having a solder-on-pad structure
A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a...
US-9,972,589 Integrated circuit package substrate with microstrip architecture and electrically grounded surface conductive...
Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive...
US-9,972,588 Semiconductor device
In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality...
US-9,972,587 Signal transmission device using electromagnetic resonance coupler
A signal transmission device comprises: a first lead frame having a first major surface and a second major surface opposite to the first major surface; a second...
US-9,972,586 Semiconductor device and authentication system
In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in...
US-9,972,585 Semiconductor device having features to prevent reverse engineering
An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the...
US-9,972,584 Chip package and manufacturing method thereof
A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface...
US-9,972,583 Durable, heat-resistant multi-layer coatings and coated articles
An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a...
US-9,972,582 Warpage balancing in thin packages
Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the...
US-9,972,581 Routing design of dummy metal cap and redistribution line
A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an...
US-9,972,580 Semiconductor package and method for fabricating the same
A semiconductor package includes a stack structure, a mold layer disposed on at least one sidewall of the stack structure, a redistribution line electrically...
US-9,972,579 Composite magnetic sealing material and electronic circuit package using the same
Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blend ratio of 50 vol. % or...
US-9,972,578 Stacked die ground shield
The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices...
US-9,972,577 EMI absorber ring
An electromagnetic interference absorber for an integrated circuit is provided. The absorber includes a geometric ring of electromagnetic energy absorbing...
US-9,972,576 Semiconductor chip package comprising side wall marking
The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body...
US-9,972,575 Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,972,574 Mark forming method, mark detecting method, and device manufacturing method
A mark forming method includes: exposing a wafer with a mask image to form first and second resist marks that have different shapes than one another based on a...
US-9,972,573 Wafer-level packaged components and methods therefor
Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of...
US-9,972,572 Semiconductor device having a barrier layer
Provided is a semiconductor device including a semiconductor substrate, an electrode provided on a front surface of the semiconductor substrate, where the...
US-9,972,571 Logic cell structure and method
The semiconductor structure includes a semiconductor substrate; field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices...
US-9,972,570 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a...
US-9,972,569 Robust low inductance power module package
A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality...
US-9,972,568 Stretchable semiconductor packages and semiconductor devices including the same
A semiconductor package includes a molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member....
US-9,972,567 Multilayer substrate, component mounted board, and method for producing component mounted board
A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal...
US-9,972,566 Interconnect array pattern with a 3:1 signal-to-ground ratio
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of...
US-9,972,565 Lateral vias for connections to buried microconductors
The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via...
US-9,972,564 Layer structure for mounting semiconductor device and fabrication method thereof
A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the...
US-9,972,563 Plated terminals with routing interconnections semiconductor device
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
US-9,972,561 QFN package with grooved leads
The present invention relates to a semiconductor package and a method for forming a semiconductor package. A lead frame adapted to a semiconductor package...
US-9,972,560 Lead frame and semiconductor device
A lead frame includes a first lead frame including a first lead; a second lead frame including a second lead, the second lead frame being stacked on the first...
US-9,972,559 Signal block and double-faced cooling power module using the same
A signal block and a double-faced cooling power module that uses the signal block is provided. The signal block includes a plurality of signal clips that are...
US-9,972,558 Leadframe package with side solder ball contact and method of manufacturing
The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls...
US-9,972,557 Integrated circuit (IC) package with a solder receiving area and associated methods
A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die...
US-9,972,556 Metal cored solder decal structure and process
A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top...
US-9,972,555 Semiconductor device and method of manufacturing same
To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the...
US-9,972,554 Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof
A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device...
US-9,972,553 Packaging system with cleaning channel and method of making the same
A packaging structure and method for surface mount integrated circuits reduces electrochemical migration (ECM) problems by including one or more cleaning...
US-9,972,550 Source/drain epitaxial electrical monitor
A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure includes...
US-9,972,549 Display device
A display device includes a plurality of pixel repairing blocks and each pixel repairing block includes a first sub-pixel unit and a second sub-pixel unit. The...
US-9,972,548 FinFET electrical characterization with enhanced hall effect and probe
A method of proving inline characterization of electrical properties of a fin-shaped field effect transistor (finFET) is provided. Embodiments include applying...
US-9,972,547 Measurement method, manufacturing method of device, and measurement system
According to one embodiment, there is provided a measurement method. The method includes measuring an amount of overlay shift between a first layer and a second...
US-9,972,546 Etching time detection means and method for etching device
An etching time detection means and an etching time detection method for an etching device. The detection means comprises: a light wave emitter fixed on one...
US-9,972,545 System and method for a field-effect transistor with dual vertical gates
A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first...
US-9,972,544 Semiconductor device with conductive pattern on insulating line pattern on spacer on field insulating film in...
A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first...
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