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Patent # Description
US-9,971,733 Scalable 2.5D interface circuitry
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each...
US-9,971,732 Public wireless network performance management system with mobile device data collection agents
Data collection agent associated with a mobile device movable within a mobile communications environment that includes at least one available network...
US-9,971,731 Asynchronous transceiver for on-vehicle electronic device
An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device...
US-9,971,730 Link layer to physical layer (PHY) serial interface
A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer...
US-9,971,728 Electrical connectors
A connection system includes a flippable cable connector (7) for connecting wires in a cable (5) to a complementary host connector located at a host device (4),...
US-9,971,727 Universal I/O signal interposer system
A universal I/O interposer system for processing an I/O signal transmitted between an I/O field device and a controller, the system includes a base connected...
US-9,971,726 Session-level-restriction for universal serial bus storage devices
A system and method of implementing SLR for a USB device of an information handling system is disclosed herein. An OS may load a disk driver stack and a volume...
US-9,971,725 Semiconductor device that employs SATA power supply terminals for data transmission
A semiconductor device includes a substrate having a serial advanced technology attachment (SATA) connector that has a plurality of power supply terminals and a...
US-9,971,724 Optimal multi-core network architecture
A multicore processor system and a method of operating the system defines a processor partition (which may include one or more processor cores) as a network...
US-9,971,723 Device and system for bridging electrical signals between SIM card and mobile device and providing service to...
A device and a system for bridging electrical signals between a SIM card and a mobile device and providing a service to the mobile device are disclosed. The...
US-9,971,722 Onboard apparatus, and onboard communication system
An onboard apparatus comprising a connection portion, a control block, and a bus switch is provided. The connection portion connects with an external device...
US-9,971,721 Method and apparatus for controlling performance of electronic device
A method for controlling performance of an electronic device is provided. The method includes sensing user input, predicting user input speed, and controlling...
US-9,971,720 Distributed credit FIFO link of a configurable mesh data bus
An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar...
US-9,971,719 System and circuit using USB Type-C interface
A system using a USB Type-C interface is provided. This system not only transmits the normal USB signal but also supports a DisplayPort Alternate Mode....
US-9,971,718 Differential amplitude detector
An example embodiment includes an idle state detection circuit. The idle state detection circuit includes a bias current loop, a rectifying circuit loop, a...
US-9,971,717 Bus interface circuit
According to an embodiment, a bus interface circuit disposed in each of a plurality of slave devices to which a common data channel and a clock channel are...
US-9,971,716 Method, system and architecture for bus transaction logger
A computing device includes at least one master unit; at least one slave unit; an interconnect structure configured to route transactions from the at least one...
US-9,971,715 Communication device and link establishment method
A slave device is realized that establishes a link with a master device or another slave device such that a large link delay hardly occurs. The slave device...
US-9,971,714 Device interfacing
Many devices may comprise interfaces, such as serial interfaces, over which configuration and/or enablement/disablement of device features may be provided to...
US-9,971,713 Multi-petascale highly efficient parallel supercomputer
A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each...
US-9,971,712 Electronic device and operating method thereof
A method for operating an electronic device is provided. In the method, an electronic cover is connected. Configuration information of the electronic cover is...
US-9,971,711 Tightly-coupled distributed uncore coherent fabric
Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates...
US-9,971,710 Optimizing data transfers between heterogeneous memory arenas
Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data...
US-9,971,709 Data migration techniques
Described are techniques for migrating data. A source data storage system includes a source device and a target data storage system includes a target device. A...
US-9,971,708 System and method for application migration between docking station and dockable device
Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes...
US-9,971,707 Protection key management and prefixing in virtual address space legacy emulation system
A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key...
US-9,971,706 System and method for logical deletion of stored data objects
Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation...
US-9,971,705 Virtual memory address range register
Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory...
US-9,971,704 Data compression accelerator methods, apparatus and design structure with improved resource utilization
Methods, apparatus and design structures are provided for improving resource utilization by data compression accelerators. An exemplary apparatus for...
US-9,971,703 Technologies for position-independent persistent memory pointers
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing...
US-9,971,702 Nested exception handling
An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device...
US-9,971,701 Method to share a coherent accelerator context inside the kernel
Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is...
US-9,971,700 Cache with address space mapping to slice subsets
A processing device includes a cache implementing a set of at least three cache slices. Each cache slice is to store a corresponding set of cache lines. The...
US-9,971,699 Method to control cache replacement for decoupled data fetch
A method, computer readable medium, and system are disclosed for decoupling data pre-fetch from demand loads. The method includes the steps of receiving, by a...
US-9,971,698 Using access-frequency hierarchy for selection of eviction destination
A method includes, in a computing system in which one or more workloads access memory pages in a memory, defining multiple memory-page lists, and specifying for...
US-9,971,697 Nonvolatile memory module having DRAM used as cache, computing system having the same, and operating method thereof
A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory,...
US-9,971,696 File-based client side cache
A file-system filter driver is attached to each cache volume containing a cache and a source volume containing a source file. The file-system filter driver...
US-9,971,695 Apparatus and method for consolidating memory access prediction information to prefetch cache memory data
An apparatus is connected to a main memory, includes a cache memory holding data and a memory storing prediction information in plural areas thereof. The...
US-9,971,694 Prefetch circuit for a processor with pointer optimization
In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy...
US-9,971,693 Prefetch tag for eviction promotion
Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching...
US-9,971,692 Supporting concurrent operations at fine granularity in a caching framework
In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is...
US-9,971,691 Selevtive application of interleave based on type of data to be stored in memory
Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a...
US-9,971,690 Transactional memory operations with write-only atomicity
Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a...
US-9,971,689 Invoking input/output (I/O) threads and demote threads on processors to demote tracks from a cache
Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads and demote threads on processors to demote tracks from a...
US-9,971,688 Apparatus and method for accelerating operations in a processor which uses shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
US-9,971,687 Operation of a multi-slice processor with history buffers storing transaction memory state information
A multi-slice processor that includes execution slices, and a history buffer, where the history buffer includes a plurality of entries, where at least one of...
US-9,971,686 Vector cache line write back processors, methods, systems, and instructions
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache...
US-9,971,685 Wear leveling based on a swapping operation between sets of physical block addresses of a non-volatile memory
A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical...
US-9,971,684 Self-configurable device for interleaving/deinterleaving data frames
A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with...
US-9,971,683 Automatic computer memory management coordination across a group of servers
A method of automatic memory management on a group of servers, the group of servers operably coupled to a coordinating program. The method comprises a first...
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