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Patent # Description
US-9,985,137 Semiconductor device having a decomposed aliphatic polycarbonate layer
It is an object of the invention to provide a thin film transistor and a method for producing the same, which will easily achieve self-aligned formation of a...
US-9,985,136 Semiconductor device
According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region...
US-9,985,135 Replacement low-k spacer
A semiconductor structure including a semiconductor material portion located on a substrate and extending along a lengthwise direction, a gate stack overlying a...
US-9,985,134 FinFETs and methods of forming FinFETs
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric...
US-9,985,133 Protection layer on fin of fin field effect transistor (FinFET) device structure
A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from...
US-9,985,132 Semiconductor device and fabricating method of a gate with an epitaxial layer
In some embodiments, a semiconductor device and a fabricating method thereof are provided. The method can comprise: providing a semiconductor substrate; forming...
US-9,985,131 Source/drain profile for FinFET
An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is...
US-9,985,130 Salicide formation on replacement metal gate finFET devices
A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a...
US-9,985,129 High-voltage metal-oxide-semiconductor transistor and fabrication method thereof
A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer...
US-9,985,128 Semiconductor device
A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first...
US-9,985,127 Semiconductor device including a mesa groove and a recess groove
To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field...
US-9,985,126 Semiconductor device comprising a first gate electrode and a second gate electrode
A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a...
US-9,985,125 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding...
US-9,985,124 Silicon carbide semiconductor device
The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer,...
US-9,985,122 Semiconductor structures
A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (PMID) layer and a composite layer is disclosed. The PMID layer is above...
US-9,985,121 P-type diamond gate-GaN heterojunction FET structure
A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom...
US-9,985,120 Bipolar transistor
Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided...
US-9,985,119 Image sensor with reduced spectral and optical crosstalk and method for making the image sensor
An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer...
US-9,985,118 Method for manufacturing semiconductor device
It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another...
US-9,985,117 Method and structure for forming dielectric isolated finFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin...
US-9,985,116 Method for processing polysilicon thin film and method for fabricating thin film transistor
A method for processing a polysilicon thin film and a method for fabricating a thin film transistor are provided. The method for processing a polysilicon thin...
US-9,985,115 Vertical transistor fabrication and devices
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first...
US-9,985,114 Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low...
A method of forming a semiconductor device that includes providing a plurality of fin structures, wherein a surface of the fin structures has a first...
US-9,985,113 Fabrication process for mitigating external resistance of a multigate device
A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material,...
US-9,985,112 Sloped finFET with methods of forming same
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a...
US-9,985,111 Structure and method for a field effect transistor
A method of forming a semiconductor structure includes forming a shallow trench isolation (STI) feature in a semiconductor substrate. An active region is...
US-9,985,110 Semiconductor process
A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide...
US-9,985,109 FinFET with reduced parasitic capacitance
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed...
US-9,985,108 Semiconductor device and method for manufacturing semiconductor device including Al electrode formed on...
An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an Al.sub.xGa.sub.(1-x)N layer AGN...
US-9,985,107 Method and structure for forming MOSFET with reduced parasitic capacitance
A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k...
US-9,985,106 Semiconductor devices utilizing spacer structures
Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field...
US-9,985,105 Method of manufacturing a PMOS transistor comprising a dual work function metal gate
The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer...
US-9,985,104 Contact first replacement metal gate
A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on...
US-9,985,103 Method of forming high electron mobility transistor
A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer...
US-9,985,102 Methods for producing improved crystallinity group III-nitride crystals from initial group III-nitride seed by...
The present invention discloses methods to create higher quality group III-nitride wafers that then generate improvements in the crystalline properties of...
US-9,985,101 Encapsulated nanostructures and method for fabricating
Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can...
US-9,985,100 Localized and self-aligned punch through stopper doping for finFET
A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the...
US-9,985,099 Semiconductor device with low band-to-band tunneling
The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source...
US-9,985,098 Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor...
US-9,985,097 Integrated capacitors with nanosheet transistors
A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same...
US-9,985,096 High thermal budget compatible punch through stop integration using doped glass
A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and...
US-9,985,095 Lateral MOSFET with buried drain extension layer
An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the...
US-9,985,094 Super junction with an angled trench, transistor having the super junction and method of making the same
A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further...
US-9,985,093 Trench-gate type semiconductor device and manufacturing method therefor
There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a...
US-9,985,092 PowerMOS
A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a...
US-9,985,090 Semiconductor device with low lifetime region
In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region...
US-9,985,089 Vertical MIM capacitor
Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal...
US-9,985,088 Metal resistors having nitridized metal surface layers with different nitrogen content
A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The...
US-9,985,087 Display device with panel test circuit
The present patent application is related to the field of display devices, and provides a display device with panel test circuit the attenuation of data voltage...
US-9,985,086 Flexible display device with space reducing wire configuration
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size...
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