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Patent # Description
US-9,985,035 Semiconductor memory structure
A semiconductor memory structure includes a substrate including a memory cell region and a cell edge region adjacent to the memory cell region. Active regions...
US-9,985,034 Method of manufacturing a semiconductor device
A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first...
US-9,985,033 Semiconductor device including capacitor
A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a...
US-9,985,032 Selectively degrading current resistance of field effect transistor devices
A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material...
US-9,985,031 Integrated circuit and manufacturing method thereof
An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor...
US-9,985,030 FinFET semiconductor device having integrated SiGe fin
A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially...
US-9,985,028 Diluted drift layer with variable stripe widths for power transistors
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift...
US-9,985,027 Stable multiple threshold voltage devices on replacement metal gate CMOS devices
A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is...
US-9,985,026 Transistor, integrated circuit and method of fabricating the same
A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source...
US-9,985,025 Active pattern structure and semiconductor device including the same
An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and...
US-9,985,024 Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
US-9,985,023 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
US-9,985,022 Electronic device including a cascode circuit having principal drive and bypass transistors
An electronic device can include a first transistor including a first gate electrode; and a second transistor including a second gate electrode. The first and...
US-9,985,021 Shallow trench isolation recess process flow for vertical field effect transistor fabrication
A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a...
US-9,985,020 Semiconductor structure and manufacturing method thereof
A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer...
US-9,985,019 Semiconductor structure with high-voltage and low-voltage CMOS devices and method for manufacturing the same
A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the...
US-9,985,018 Embedded tungsten resistor
A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR...
US-9,985,017 Semiconductor device comprising a clamping structure
Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected...
US-9,985,016 Charge pump circuit for providing multiplied voltage
A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel...
US-9,985,015 Semiconductor device having improved core and input/output device reliability
A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k...
US-9,985,014 Minimum track standard cell circuits for reduced area
Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio...
US-9,985,013 Package-on-package structure and methods for forming the same
A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls...
US-9,985,012 Display apparatus and a method of manufacturing the same
A display apparatus includes a flexible substrate, a light-emitting diode (LED), and a partitioning wall pattern. The flexible substrate includes a ...
US-9,985,011 Method for producing an optoelectronic semiconductor chip
A method for producing an optoelectronic semiconductor chip is disclosed. A semiconductor body has a pixel area, which has at least two different subpixel...
US-9,985,010 System, apparatus, and method for embedding a device in a faceup workpiece
An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound...
US-9,985,009 Manufacturing method of LED light emitting device
Disclosed are an LED light emitting device and its manufacturing method. A blue LED chip specification is selected, a green phosphor and the blue LED chip are...
US-9,985,007 Package on-package devices with multiple levels and methods therefor
Package-on-package ("PoP") devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount...
US-9,985,006 Semiconductor structure and manufacturing method thereof
The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the...
US-9,985,005 Chip package-in-package
An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the...
US-9,985,004 Packaging a substrate with an LED into an interconnect structure only through top side landing pads on the...
Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass...
US-9,985,003 Substrate with array of LEDs for backlighting a display device
An apparatus includes a substrate and a circuit trace having a predetermined pattern disposed on the substrate. A plurality of LEDs are connected to the...
US-9,985,002 Thin stack packages
The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the...
US-9,985,001 3DIC package and methods of forming the same
A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding...
US-9,985,000 Stacked semiconductor die assemblies with die support members and associated systems and methods
Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,984,999 Packages with stacked dies and methods of forming the same
A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first...
US-9,984,998 Devices employing thermal and mechanical enhanced layers and methods of forming same
A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming...
US-9,984,997 Communication interface architecture using serializer/deserializer
A memory interface architecture uses a serializer/deserializer (SerDes) to connect a memory array on one semiconductor die to a device on another semiconductor...
US-9,984,996 Three-dimensional (3D) package structure with electronic components encapsulated by a connection structure over...
The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a...
US-9,984,995 Semiconductor package and manufacturing method thereof
A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor...
US-9,984,994 Method for bonding a hermetic module to an electrode array
A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top...
US-9,984,993 Bonding structure for semiconductor package and method of manufacturing the same
A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad...
US-9,984,991 Circuit device, electronic apparatus and moving object
In order to reduce crosstalk between analog and digital signals, a circuit device includes a vibrator element, a semiconductor device, and a package. In the...
US-9,984,990 Semiconductor device
A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor...
US-9,984,989 Semiconductor substrate and semiconductor package structure
A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and...
US-9,984,988 Flip chip assembly with connected component
A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A...
US-9,984,987 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface;...
US-9,984,986 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate, a patterned conductive layer on the substrate, a passivation layer on the substrate and surrounding the patterned...
US-9,984,985 Semiconductor package device with antenna array
The present disclosure provides for a semiconductor package device. The semiconductor package device includes a substrate, a first antenna, an electronic...
US-9,984,984 Semiconductor element mounting board
A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads...
US-9,984,983 Semiconductor packages with thermal-enhanced conformal shielding and related methods
The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially...
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