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Patent # Description
US-9,984,982 Device and method for generating identification key
The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the...
US-9,984,981 Packages with interposers and methods for forming the same
A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer....
US-9,984,980 Molded lead frame device
A molded lead frame device includes a plurality of lead frame units and a molding layer. Each of the lead frame units includes an array of leads. Each of the...
US-9,984,979 Fan-out semiconductor package and method of manufacturing the same
The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first...
US-9,984,978 Body-bias voltage routing structures
In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.
US-9,984,977 Semiconductor constructions
Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the...
US-9,984,976 Interconnect structures and methods of formation
Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect...
US-9,984,975 Barrier structure for copper interconnect
A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a...
US-9,984,974 Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric...
A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate...
US-9,984,973 Method of manufacturing semiconductor device and semiconductor device
Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time,...
US-9,984,972 Semiconductor device and method of manufacturing the same
A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an...
US-9,984,971 Methods of forming metal pad structures over TSVS to reduce shorting of upper metal layers
Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad...
US-9,984,970 Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced...
An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent...
US-9,984,969 Semiconductor devices, multi-die packages, and methods of manufacure thereof
Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first...
US-9,984,968 Semiconductor package and related methods
Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect...
US-9,984,967 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive...
US-9,984,966 Semiconductor device having fuse elements
Provided is a semiconductor device preventing readhesion of conductive body which forms fuse elements and breakage of the fuse elements. The semiconductor...
US-9,984,965 Inductor system and method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors....
US-9,984,964 Integrated circuit having slot via and method of forming the same
An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second...
US-9,984,963 Cobalt-containing conductive layers for control gate electrodes in a memory structure
A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack...
US-9,984,962 Systems and methods for hybrid flexible electronics with rigid integrated circuits
Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects....
US-9,984,961 Chip-size, double side connection package and method for manufacturing the same
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post...
US-9,984,960 Integrated fan-out package and method of fabricating the same
Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of...
US-9,984,959 Semiconductor device and manufacturing method thereof
An object of the present invention is to improve the performance of a semiconductor device that transmits signals using inductive coupling of inductors. A...
US-9,984,958 Leadframe and semiconductor device
A semiconductor device includes a leadframe, a semiconductor chip, and an encapsulation resin encapsulating the leadframe and the semiconductor chip. The...
US-9,984,956 Through electrode, manufacturing method thereof, and semiconductor device and manufacturing method thereof
Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical...
US-9,984,955 Lightweight liquid-cooling-plate assembly having plastic frame and heat dissipation system using same
The present invention relates to a lightweight liquid-cooling-plate assembly having a plastic frame and a heat dissipation system using the same. The...
US-9,984,954 Phase changing on-chip thermal heat sink
A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the...
US-9,984,953 Semiconductor assembly having a press pack stack
A semiconductor assembly includes a stack with a semiconductor module and a cooler, wherein the semiconductor module is provided in contact with the cooler. A...
US-9,984,952 Thermally enhanced semiconductor package having field effect transistors with back-gate feature
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally...
US-9,984,951 Sintered multilayer heat sinks for microelectronic packages and methods for the production thereof
Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal...
US-9,984,950 Semiconductor package and method for manufacturing the same
Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor...
US-9,984,949 Surface passivation having reduced interface defect density
Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect...
US-9,984,948 High voltage power electronics module for subsea applications under high hydrostatic pressure and temperature...
A power electronics module includes: a baseplate, a power semiconductor chip arranged on the baseplate, and an encapsulation structure arranged on the baseplate...
US-9,984,947 Fingerprint sensor and manufacturing method thereof
A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various...
US-9,984,946 Semiconductor device and method for manufacturing the same
An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing...
US-9,984,945 Semiconductor chip
A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack...
US-9,984,944 Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such...
US-9,984,943 Systems and methods for aligning and coupling semiconductor structures
In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second...
US-9,984,942 Method and device for leveling a substrate stack
A method for equalizing the thickness variation of a substrate stack which is comprised of a product substrate and a carrier substrate and which is connected in...
US-9,984,941 Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers
A semiconductor material stack of, from bottom to top, a first semiconductor material having a first lattice constant and a second semiconductor material having...
US-9,984,940 Selective and conformal passivation layer for 3D high-mobility channel devices
A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is...
US-9,984,939 Well implantation process for FinFET device
A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate...
US-9,984,938 Integrate circuit with nanowires
A method includes providing a substrate having a first gate region for a first device and a second gate region for a second device, the first and second gate...
US-9,984,937 Vertical silicon/silicon-germanium transistors with multiple threshold voltages
A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins...
US-9,984,936 Methods of forming an isolated nano-sheet transistor device and the resulting device
A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the...
US-9,984,935 Uniform dielectric recess depth during fin reveal
A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is...
US-9,984,934 Method of manufacturing a semiconductor device with wider sidewall spacer for a high voltage MISFET
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The...
US-9,984,933 Silicon liner for STI CMP stop in FinFET
A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is...
US-9,984,932 Semiconductor fin loop for use with diffusion break
A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin...
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