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Patent # Description
US-9,991,385 Enhanced volume control by recess profile control
The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a...
US-9,991,384 Semiconductor device including fin structures and manufacturing method thereof
A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes...
US-9,991,383 Semiconductor component and manufacturing method thereof
A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that...
US-9,991,382 Vertical field effect transistor with abrupt extensions at a bottom source/drain structure
A semiconductor structure is provided that includes a vertical transport field effect transistor located on sidewall surfaces of a semiconductor fin. The...
US-9,991,381 Semiconductor device having fin-shaped semiconductor layer
A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first...
US-9,991,379 Semiconductor device with a gate insulating film formed on an inner wall of a trench, and method of...
A semiconductor device includes a semiconductor substrate, which includes: a drift region that has a first conductivity type; a body region that has a second...
US-9,991,378 Trench power semiconductor device
A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer...
US-9,991,377 Trench FET with ruggedness enhancement regions
According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first...
US-9,991,376 High voltage MOSFET devices and methods of making the devices
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+...
US-9,991,375 Metal gate electrode of a semiconductor device
The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device...
US-9,991,374 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes sequentially stacking a first epitaxial layer, a sacrificial layer, a second epitaxial layer, and a...
US-9,991,373 Semiconductor device
In an embodiment, a semiconductor device includes a substrate, a Group III nitride based transistor arranged on a front surface of the substrate, and a...
US-9,991,372 Device with channel having varying carrier concentration
A semiconductor device including a device channel with a gate-drain region having a carrier concentration that varies laterally along a direction from the gate...
US-9,991,371 Semiconductor device including two-dimensional material
A semiconductor device includes a substrate, a two-dimensional (2D) material layer formed on the substrate and having a first region and a second region...
US-9,991,370 Methods and systems for ultra-high quality gated hybrid devices and sensors
High electron mobility leads to better device performance and today is achieved by fabricating "gated devices" within a high-mobility two-dimensional electron...
US-9,991,369 ESD protection SCR device
An ESD protection SCR device includes a semiconductor substrate, an epitaxial layer, device isolation layers, an n-type well formed in an anode region, a first...
US-9,991,368 Vertical BJT for high density memory
Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled...
US-9,991,367 Bipolar junction transistor
A bipolar junction transistor (BJT) includes an emitter region, a base region surrounding the emitter region, and a collector region surrounding the base...
US-9,991,366 Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET
After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose...
US-9,991,365 Forming vertical transport field effect transistors with uniform bottom spacer thickness
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a...
US-9,991,364 Transistor strain-inducing scheme
A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the...
US-9,991,363 Contact etch stop layer with sacrificial polysilicon layer
A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During...
US-9,991,362 Semiconductor device including tungsten gate and manufacturing method thereof
In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron...
US-9,991,361 Methods for performing a gate cut last scheme for FinFET semiconductor devices
A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first...
US-9,991,360 Method for forming III-V semiconductor structures including aluminum-silicon nitride passivation
A method for fabricating a semiconductor structure includes forming a semiconductor layer over a substrate and forming an aluminum-silicon nitride layer upon...
US-9,991,359 Vertical transistor gated diode
After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped...
US-9,991,358 Semiconductor device with metal-insulator-semiconductor structure
A semiconductor device according to an embodiment includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the...
US-9,991,357 Semiconductor devices with gate electrodes on separate sets of high-k dielectric layers
A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate...
US-9,991,356 Integrated circuits devices with counter-doped conductive gates
Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a...
US-9,991,355 Implantation formed metal-insulator-semiconductor (MIS) contacts
A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method...
US-9,991,354 Metal nitride alloy contact for semiconductor
Systems and methods are provided that enable the production of semiconductor devices having a metal nitride layer in direct contact with a semiconductor layer...
US-9,991,353 Semiconductor device
Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation...
US-9,991,352 Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device
A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of...
US-9,991,351 Method of making a semiconductor device using a dummy gate
A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming...
US-9,991,350 Low resistance sinker contact
An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into...
US-9,991,349 Semiconductor device and method for manufacturing semiconductor device
Certain embodiments provide a semiconductor device including a semiconductor substrate, a semiconductor element, and wiring. The semiconductor element has an...
US-9,991,348 Array substrate with reduced flickering, method for manufacturing the same and display device
An array substrate includes a gate electrode and a source electrode arranged on a base substrate of the array substrate. The source electrode has a first end...
US-9,991,347 Semiconductor device having a cavity
A power semiconductor device includes a semiconductor substrate having a drift region, a gate electrode trench in the semiconductor substrate and a field...
US-9,991,346 Semiconductor structure comprising an active semiconductor layer of the III-V type on a buffer layer stack and...
A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one...
US-9,991,345 Semiconductor device
There is provided a semiconductor device comprising a group III nitride semiconductor layer; a gate insulating film formed on the group III nitride...
US-9,991,344 Silicon carbide EPI wafer and method for manufacturing same
An embodiment provides: a method for manufacturing a silicon carbide epi wafer, the method comprising the steps of preparing a wafer, applying a reaction gas to...
US-9,991,343 LDD-free semiconductor structure and manufacturing method of the same
The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region...
US-9,991,342 Electronic device containing nanowire(s), equipped with a transition metal buffer layer, process for growing at...
The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said...
US-9,991,341 Method for treating a gallium nitride layer comprising dislocations
A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its...
US-9,991,340 Mechanical stress-decoupling in semiconductor device
According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device....
US-9,991,339 Bulk to silicon on insulator device
A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of...
US-9,991,338 Electronic device including a conductive structure surrounded by an insulating structure
An electronic device can include a substrate and an insulating structure laterally surrounded by the substrate. In an aspect, the electronic device can include...
US-9,991,337 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region;...
US-9,991,336 Semiconductor device, method for manufacturing the same, and power conversion system
An anode electrode and a cathode electrode formed on a silicon semiconductor substrate, p-type layer formed next to the anode electrode, an n-type layer formed...
US-9,991,335 Semiconductor device having a polarization super junction field effect transistor, electric equipment,...
Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage...
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