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Patent # Description
US-9,991,282 Three-dimensional memory device having passive devices at a buried source line level and method of making thereof
A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the...
US-9,991,281 Semiconductor devices and methods of manufacturing the same
A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide...
US-9,991,280 Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and...
An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of...
US-9,991,279 Method for manufacturing electronic device using sacrificial layer
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench,...
US-9,991,278 Non-volatile memory device
According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first...
US-9,991,277 Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof
A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack...
US-9,991,276 Semiconductor device
According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a...
US-9,991,275 Semiconductor memory device
A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate,...
US-9,991,274 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating...
US-9,991,273 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,991,272 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a...
US-9,991,271 Integrated circuit device including vertical memory device and method of manufacturing the same
In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the...
US-9,991,270 Semiconductor device and manufacturing method for same
A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of...
US-9,991,269 Non-overlapped-extension-implantation nonvolatile memory device capable of being treated with anti-fuse operation
The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation....
US-9,991,268 SRAM cell structure
A static random access memory (SRAM) cell and a SRAM cell structure are provided. The SRAM cell includes a first pull-down transistor, a first pull-up...
US-9,991,267 Forming eDRAM unit cell with VFET and via capacitance
A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor)...
US-9,991,266 Semiconductor memory device and semiconductor memory array comprising the same
A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first...
US-9,991,264 Integrated circuit device and method of manufacturing the same
An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated...
US-9,991,263 Semiconductor device
The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters...
US-9,991,262 Semiconductor device on hybrid substrate and method of manufacturing the same
A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin...
US-9,991,261 Gate-all-around nanowire device and method for manufacturing such a device
The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for...
US-9,991,260 HVMOS reliability evaluation using bulk resistances as indices
A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the...
US-9,991,259 Semiconductor device
Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first...
US-9,991,258 FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator
Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin...
US-9,991,257 Semiconductor device having fin active regions and method of fabricating the same
A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate...
US-9,991,256 Semiconductor structure and manufacturing method thereof
A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are...
US-9,991,255 FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces
Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a...
US-9,991,254 Forming horizontal bipolar junction transistor compatible with nanosheets
A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate....
US-9,991,253 Protection element, protection circuit, and semiconductor integrated circuit
To provide a protection element in which an increase in current due to off-state leakage can be reduced while a drive current can be ensured during an ESD...
US-9,991,252 Semiconductor device comprising electrostatic discharge protection structure
A semiconductor device includes a semiconductor body having first and second opposing surfaces, a first isolation layer on the first surface of the...
US-9,991,251 Semiconductor device
A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a...
US-9,991,250 Electrostatic discharge devices and method of making the same
In one embodiment, electrostatic discharge (ESD) devices are disclosed.
US-9,991,249 Integrated circuit and computer-implemented method of manufacturing the same
A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit,...
US-9,991,248 Method and device of pop stacking for preventing bridging of interposer solder balls
A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has...
US-9,991,247 Semiconductor device packages, packaging methods, and packaged semiconductor devices
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device...
US-9,991,246 Contoured package-on-package joint
A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having...
US-9,991,244 Method for forming hybrid bonding with through substrate via (TSV)
Method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor wafer and a second...
US-9,991,243 Integrated circuit assembly that includes stacked dice
An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member...
US-9,991,242 Semiconductor device, method of manufacturing a semiconductor device, and positioning jig
A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a...
US-9,991,241 Light emitting device package
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and...
US-9,991,240 Display apparatus and method of manufacturing the same
A display apparatus includes: a display substrate; a light-emitting diode ("LED") disposed on the display substrate and which emits light; a passivation layer...
US-9,991,239 Method of embedding WLCSP components in e-WLB and e-PLB
Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a...
US-9,991,238 LED light source for automotive application
Proposed is a light source comprising first and second LED light sources. Each of the first and second LED light sources have: a semiconductor diode structure...
US-9,991,237 Light emitting device
A light emitting device includes a base, a first light emitting element, a second light emitting element, and a sealing member. The first light emitting element...
US-9,991,236 LED lamp device having a fluorescent element shaped for uniform light conversion
An LED lamp device includes a plurality of LED elements separately mounted on a substrate and effective to emit light having a first wavelength. A fluorescent...
US-9,991,235 Package on-package devices with upper RDL of WLPS and methods therefor
Package-on-package ("PoP") devices with upper RDLs of WLP ("WLP") components and methods therefor are disclosed. In a PoP device, a first IC die is surface...
US-9,991,234 Semiconductor package
A semiconductor package includes a substrate, a plurality of semiconductor chips stacked on the substrate, and a plurality of bonding layers bonded to lower...
US-9,991,233 Package-on-package devices with same level WLP components and methods therefor
Package-on-package ("PoP") devices with same level wafer-level packaged ("WLP") components and methods therefor are disclosed. In a PoP device, a first...
US-9,991,232 Package and packaging process of a semiconductor device
A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned...
US-9,991,231 Stacked die integrated circuit
An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending...
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