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Patent # Description
US-9,991,180 Semiconductor device for reducing self-inductance
A semiconductor device includes: a resin case that houses a semiconductor element; a parallel plate that is disposed inside the resin case while being connected...
US-9,991,179 Method of manufacturing semiconductor device
Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a...
US-9,991,178 Interposer and electrical testing method thereof
An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the...
US-9,991,177 Method and arrangement for analyzing a semiconductor element and method for manufacturing a semiconductor component
According to the improved concept, a method for analyzing a semiconductor element comprising polymer residues located on a surface of the semiconductor element...
US-9,991,176 Non-destructive acoustic metrology for void detection
Advanced interconnect technologies such as Through Silicon Vias (TSVs) have become an integral part of 3-D integration. Methods and systems and provided for...
US-9,991,175 Method for estimating depth of latent scratches in SiC substrates
This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching...
US-9,991,174 Method and system of measuring semiconductor device and method of fabricating semiconductor device using the same
The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data...
US-9,991,173 Bidirectional semiconductor device for protection against electrostatic discharges
An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against...
US-9,991,172 Forming arsenide-based complementary logic on a single substrate
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si)...
US-9,991,171 Semiconductor device and integrated circuit
A semiconductor device and an integrated circuit are provided. The semiconductor device includes a field effect transistor, a negative capacitor and a control...
US-9,991,170 Integrating a planar field effect transistor (FET) with a vertical FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
US-9,991,169 Semiconductor device and formation thereof
A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an...
US-9,991,168 Germanium dual-fin field effect transistor
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
US-9,991,167 Method and IC structure for increasing pitch between gates
Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present...
US-9,991,166 Wimpy device by selective laser annealing
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
US-9,991,165 Asymmetric source/drain epitaxy
A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure...
US-9,991,164 Semiconductor die singulation methods
Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first...
US-9,991,163 Small-aperture-ratio display with electrical component
A small-aperture-ratio display includes a display substrate and a plurality of spatially separated pixel elements distributed over the display substrate. Each...
US-9,991,162 Semiconductor device and manufacturing method thereof
A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to...
US-9,991,161 Alternate plating and etching processes for through hole filling
A method for filling a through hole (TH) located on a substrate is provided. The TH is a continuous channel having an upper rim, a lower rim and an interior...
US-9,991,160 Process of forming semiconductor device having interconnection formed by electro-plating
A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a...
US-9,991,159 Semiconductor device manufacture method
According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes...
US-9,991,158 Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device
A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled...
US-9,991,157 Method for depositing a diffusion barrier layer and a metal conductive layer
We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which...
US-9,991,156 Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure...
US-9,991,155 Local trap-rich isolation
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize...
US-9,991,154 Method for fabricating a fin field effect transistor and a shallow trench isolation
A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500...
US-9,991,153 Substrate support bushing
In one embodiment, a substrate support bushing for a lift pin used in a semiconductor processing chamber is provided. The bushing includes an elongated housing...
US-9,991,152 Wafer-handling end effectors with wafer-contacting surfaces and sealing structures
Wafer-handling end effectors and semiconductor manufacturing devices that include and/or are utilized with wafer-handling end effectors are disclosed herein....
US-9,991,151 Chip spacing maintaining apparatus
A chip spacing maintaining apparatus for maintaining the spacing between any adjacent ones of a plurality of chips obtained by dividing a workpiece attached to...
US-9,991,150 Procedure of processing a workpiece and an apparatus designed for the procedure
The present invention provides a procedure of processing a workpiece such as backside grinding of a device wafer and an apparatus designed for the procedure....
US-9,991,148 Electrostatic chuck having thermally isolated zones with minimal crosstalk
A substrate support assembly includes a ceramic puck and a thermally conductive base having an upper surface that is bonded to a lower surface of the ceramic...
US-9,991,147 Wafer grounding and biasing method, apparatus, and application
A wafer grounding apparatus and method adaptable to a charged particle beam apparatus is disclosed. A wafer substrate is supported by a wafer mount. A pulse...
US-9,991,146 Detection device
The present invention provides a detection device for a cassette comprising at least one supporting unit, each supporting unit comprising a plurality of...
US-9,991,145 Plating apparatus and plating method
A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed...
US-9,991,144 Storage warehouse
A storage warehouse includes shelves, wherein first and second containers capable of being transported while placed on an attachment are stored; a warehouse-in...
US-9,991,143 Carrier transport system and transport method
Carriers to be temporarily stored are increased in number, without providing a local vehicle with a lateral transfer mechanism. Carriers are transported between...
US-9,991,142 Apparatus and method for decapsulating packaged integrated circuits
A system for decapsulating a portion of an encapsulated integrated circuit that includes copper elements has one or more containers holding specific etchant...
US-9,991,141 Substrate processing apparatus and heater cleaning method
A substrate processing apparatus includes a heater having an infrared lamp and a housing for heating an upper surface of a substrate held by a substrate holding...
US-9,991,140 Substrate heating device, substrate heating method and computer-readable storage medium
A substrate heating device includes: heating modules each having a processing vessel within which a heating plate is disposed, an gas inlet port for introducing...
US-9,991,139 Modular vertical furnace processing system
A vertical furnace processing system for processing semiconductor substrates, comprising the following modules: --a processing module including a vertical...
US-9,991,138 Etching method and etching apparatus
An etching method includes a step of etching a cobalt film formed on a surface of a target object by supplying an etching gas containing .beta.-diketone and an...
US-9,991,137 Substrate treatment method and substrate treatment device
This substrate processing method includes: a substrate rotating step of rotating a substrate around a predetermined vertical axis line at a first rotation...
US-9,991,136 Leadframe and the method to fabricate thereof
The present invention discloses a leadframe in which two conductive pillars with a high aspect ratio and the corresponding two leads of the leadframe form a 3D...
US-9,991,135 Method for fabricating a metal oxide thin film transistor
A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of...
US-9,991,134 Processing systems and methods for halide scavenging
Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for...
US-9,991,133 Method for etch-based planarization of a substrate
Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a...
US-9,991,132 Lithographic technique incorporating varied pattern materials
A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a...
US-9,991,131 Dual mandrels to enable variable fin pitch
A double masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch within different arrays. During the process, a top...
US-9,991,130 Method for manufacturing semiconductor device
A trench is formed at an exposed portion of a semiconductor substrate by performing a dry etching process with a hard mask of silicon oxide film serving as an...
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