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Patent # Description
US-9,997,486 Anisotropic conductive film including oblique region having lower curing ratio
An anisotropic conductive film has a first connection layer and a second connection layer formed on surface of the first connection layer. The first connection...
US-9,997,485 Bonding structure and method
A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the...
US-9,997,484 Semiconductor device and manufacturing method of the same
A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin...
US-9,997,483 Ball amount process in the manufacturing of integrated circuit
An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over...
US-9,997,482 Solder stud structure
A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor...
US-9,997,481 Semiconductor package with stacked semiconductor chips
A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps...
US-9,997,480 Method of forming a semiconductor device including strain reduced structure
A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on...
US-9,997,479 Method for manufacturing redistribution layer
In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top...
US-9,997,478 Circuits and antennas integrated in dies and corresponding method
Circuits and antennas integrated in dies and corresponding method. The circuits and the antennas are positioned on the front surface and the back surface of the...
US-9,997,477 Method of manufacturing semiconductor package
A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive...
US-9,997,476 Multi-die package having different types of semiconductor dies attached to the same thermally conductive flange
A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first...
US-9,997,475 Monolithic integration of III-V cells for powering memory erasure devices
A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor...
US-9,997,474 Wiring board and semiconductor device
A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the...
US-9,997,473 Chip package and method for forming the same
A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or...
US-9,997,472 Support for long channel length nanowire transistors
A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire...
US-9,997,471 Semiconductor package structure and manufacturing method thereof
A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution...
US-9,997,470 Semiconductor device and manufacturing method thereof
Embodiments include a semiconductor manufacturing method comprising, providing an object to be processed, the object including a semiconductor element, a...
US-9,997,469 Electronic package having a protruding barrier frame
An electronic package is provided, which includes: a carrier; a plurality of electronic elements disposed on the carrier; a barrier frame disposed on the...
US-9,997,468 Integrated circuit packaging system with shielding and method of manufacturing thereof
An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate...
US-9,997,467 Semiconductor packages and methods of forming the same
Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of...
US-9,997,466 Integrated circuit stack including a patterned array of electrically conductive pillars
The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer...
US-9,997,465 Semiconductor package structure
Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via...
US-9,997,464 Dummy features in redistribution layers (RDLS) and methods of forming same
An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern...
US-9,997,463 Modular interconnects for gate-all-around transistors
A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure...
US-9,997,462 Semiconductor memory devices
A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical...
US-9,997,461 Electrically conductive laminate structures
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
US-9,997,460 Formation of advanced interconnects
An advanced metal conductor structure is described. An integrated circuit device including a substrate with a patterned dielectric layer. The pattern includes a...
US-9,997,459 Semiconductor device having a barrier layer made of amorphous molybdenum nitride and method for producing such...
A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer...
US-9,997,458 Method for manufacturing germamde interconnect structures and corresponding interconnect structures
Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially...
US-9,997,457 Cobalt based interconnects and methods of fabrication thereof
An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the...
US-9,997,456 Interconnect structure having power rail structure and related method
Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction...
US-9,997,455 Device architecture and method for precision enhancement of vertical semiconductor devices
Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a...
US-9,997,454 BEOL vertical fuse formed over air gap
A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the...
US-9,997,453 Antifuse having comb-like top electrode
Antifuse structures are provided for use in applications such as field programmable gate arrays and programmable read-only memories. High aspect ratio channels...
US-9,997,452 Forming conductive plugs for memory device
Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations...
US-9,997,450 Wiring substrate and semiconductor device
A wiring substrate includes a first connection terminal and a protective insulation layer. The first connection terminal is electrically connected to a wiring...
US-9,997,449 Semiconductor device connection structure, ultrasonic module, and ultrasonic endoscope system having ultrasonic...
A semiconductor device connection structure includes: a semiconductor element having a plate shape and including an external connection electrode on a surface...
US-9,997,448 Wiring substrate
A wiring substrate includes a flexible insulation substrate, a first wiring layer formed on an upper surface of the insulation substrate, a second wiring layer...
US-9,997,447 Semiconductor devices
A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of...
US-9,997,446 Semiconductor package including a rewiring layer with an embedded chip
A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The...
US-9,997,445 Substrate interconnections for packaged semiconductor device
A "universal" substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the...
US-9,997,444 Microelectronic package having a passive microelectronic device disposed within a package body
A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the...
US-9,997,443 Through vias and methods of formation thereof
In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region...
US-9,997,442 Semiconductor device and method of manufacturing the same
A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines...
US-9,997,441 Support member, wiring substrate, method for manufacturing wiring substrate, and method for manufacturing...
A wiring substrate includes a support member, and a wiring member formed on one side of the support member. The support member includes metal foils and at least...
US-9,997,440 Protection layer for adhesive material at wafer edge
A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second...
US-9,997,439 Method for fabricating an advanced routable quad flat no-lead package
An improved leadframe assembly for use in a quad flat no lead (QFN) package is described along with a method of fabricating both the leadframe assembly and the...
US-9,997,438 Leads frames with crossing leads
An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a...
US-9,997,437 Power semiconductor module for improved thermal performance
Semiconductor module has a first member, a second member, a conductor column extending in the vertical direction between the first member and the second member...
US-9,997,436 Apparatus and method of three dimensional conductive lines
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a...
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