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Patent # Description
US-1,001,4303 Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods
Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method...
US-1,001,4302 Methods of forming memory arrays
Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material....
US-1,001,4301 Semiconductor constructions
Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces....
US-1,001,4300 Integrated circuit devices having inter-device isolation regions and methods of manufacturing the same
An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active...
US-1,001,4299 Field effect transistor device spacers
A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack...
US-1,001,4298 Method of forming field effect transistors with replacement metal gates and contacts and resulting structure
In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates...
US-1,001,4297 Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and...
One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a...
US-1,001,4296 Fin-type field effect transistors with single-diffusion breaks and method
Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break...
US-1,001,4295 Self heating reduction for analog radio frequency (RF) device
A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a...
US-1,001,4294 Semiconductor integrated circuit device having enhancement type NMOS and depression type MOS with N-type...
Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a...
US-1,001,4293 Semiconductor device
A semiconductor device of a circuit is provided. The circuit is configured to be operated under a power supply. The semiconductor device of the circuit includes...
US-1,001,4292 3D semiconductor device and structure
A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying...
US-1,001,4291 SiC crystalline on Si substrates to allow integration of GaN and Si electronics
A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a...
US-1,001,4290 Semiconductor integrated circuit
A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a...
US-1,001,4289 Electrostatic discharge protection circuits and structures and methods of manufacture
An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN...
US-1,001,4288 Ultra high voltage electrostatic discharge protection device with current gain
A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A...
US-1,001,4287 Semiconductor device
A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes...
US-1,001,4286 Stackable electronics package and method of fabricating same
An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact...
US-1,001,4285 Semiconductor devices
A semiconductor device may include a first conductive pattern disposed in a first interlayer insulating film, a second conductive pattern disposed in a second...
US-1,001,4284 Power semiconductor module for an inverter circuit and method of manufacturing the same
A semiconductor device according to the present invention includes a semiconductor chip, a conductive member for supporting the semiconductor chip, a joint...
US-1,001,4283 High heat dissipation stacked chip package structure and the manufacture method thereof
The present invention provides a semiconductor device including a first glass substrate, a first integrated chip, a first anisotropic conductive film, a second...
US-1,001,4282 3D semiconductor device and structure
An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at...
US-1,001,4281 Methods of manufacturing a semiconductor device package including a controller element
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
US-1,001,4280 Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the...
US-1,001,4279 Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities
In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on...
US-1,001,4278 Semiconductor chip and stacked semiconductor package having the same
A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the...
US-1,001,4277 Single layer low cost wafer level packaging for SFF SiP
In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded...
US-1,001,4276 Compensation of bondwires in the microwave regime
A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric...
US-1,001,4275 Method for producing a chip assemblage
One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and...
US-1,001,4274 Optimized solder pads for microelectronic components
A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the...
US-1,001,4273 Fixture to constrain laminate and method of assembly
A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip...
US-1,001,4272 Die bonding with liquid phase solder
A method of bonding a die comprising solder bumps to a substrate comprising bond pads, the method comprising the steps of heating the die from a first...
US-1,001,4271 Semiconductor structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first...
US-1,001,4270 Protrusion bump pads for bond-on-trace processing
An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion...
US-1,001,4269 Method for wafer dicing
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding...
US-1,001,4268 Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same
A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent...
US-1,001,4267 Semiconductor device and method of manufacturing the same
A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a...
US-1,001,4266 Monolithic microwave integrated circuit (MMIC) and method for forming such MMIC having rapid thermal annealing...
A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission...
US-1,001,4265 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,001,4264 Hyperfrequency housing occupying a small surface area and mounting of such a housing on a circuit
A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted...
US-1,001,4263 Package assembly for embedded die and associated techniques and configurations
Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment,...
US-1,001,4262 Method of wafer dicing for backside metallization
Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer,...
US-1,001,4261 Microchip charge patterning
A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to...
US-1,001,4260 Package structure and method for forming the same
Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method...
US-1,001,4259 Light emitting device, light emitting device package comprising light emitting device, and light emitting...
A light emitting device according to an embodiment includes a substrate; first to Mth light emitting cells (where M is a positive integer of two or more) which...
US-1,001,4258 Silicon carbide semiconductor device having gate electrode
The gate electrode is provided on the gate insulating film. The interlayer insulating film is provided to cover the gate electrode. The interlayer insulating...
US-1,001,4257 Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures
An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of...
US-1,001,4256 Unidirectional metal on layer with ebeam
Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a...
US-1,001,4255 Contacts having a geometry to reduce resistance
A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an...
US-1,001,4254 Semiconductor device
There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores...
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