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Patent # Description
US-1,001,4089 Liquid precursor compositions, preparation methods thereof, and methods for forming layer using the composition
Liquid precursor compositions are provided, along with methods of preparing the liquid precursor compositions, and methods for forming layers using the liquid...
US-1,001,4088 Method for processing liquid radioactive waste and for the recovery thereof
The invention relates to a technique for handling liquid radioactive waste from a nuclear fuel-energy cycle, and may be used in a process for processing liquid...
US-1,001,4087 Apparatus for cleaning contaminated water from radioactive materials
Apparatus and methods for treating radioactive material, in particular for cleaning radioactive contaminated water, are described. One apparatus comprises a...
US-1,001,4086 Integrated method and apparatus for remediation of uranium-contaminated soils
Apparatus and method are provided for the treatment of uranium-contaminated soil by using comprehensive joint technology. The apparatus include the pumping...
US-1,001,4085 Reuseable holder for a radioactive source capsule
This disclosure pertains to a holder for a radioactive source capsule with pivoting first and second parts, with redundant mechanisms for retention of the...
US-1,001,4084 Systems and methods for nuclear reactor vessel segmenting
Nuclear reactor vessel segmenting utilizing improved arc saw systems and methods.
US-1,001,4083 Method of refueling a nuclear reactor
A method of refueling a nuclear reactor that includes the steps of removing the reactor vessel head and upper internals to a storage location and installing a...
US-1,001,4082 Nuclear power plant and reactor building gas treatment system
A nuclear power plant according to an embodiment comprises: a reactor well; a reactor well upper lid; an operation floor; an operation floor area wall; a...
US-1,001,4081 Block-type movable reflector/moderator (RM) for nuclear reactor control
A block-type movable reflector/moderator (RM) for nuclear reactor control is disclosed. This reactor control system can be applied to all types of reactors...
US-1,001,4080 Evidence based medical record
Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a method of providing a...
US-1,001,4079 Business method for collection, processing, cryogenic storage and distribution of a biologic sample material
Methods and systems for collection, processing, cryogenic storage and distribution of a stem cell based biological sample material.
US-1,001,4078 Method and system for presenting medical contents
A method is disclosed for presenting medical contents. An embodiment of the method includes generating a pseudonymized case study from a patient study using a...
US-1,001,4077 Method and system for improving care determination
Embodiments of a method and system for improving care determination for care providers in relation to a condition of a user associated with a mobile device can...
US-1,001,4076 Baggage system, RFID chip, server and method for capturing baggage data
A baggage system includes a plurality of RFID tags affixed to baggage items, a data collection engine, client devices and backend devices. The backend devices...
US-1,001,4075 System for encouraging health support program participation
A value icon for a web-based health or health support program packages access information for a website in a value icon physically embodying the abstract...
US-1,001,4074 Failure analysis and repair register sharing for memory BIST
A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared...
US-1,001,4073 Semiconductor devices
A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal...
US-1,001,4072 Diagnosis method for diagnosing memory, transmission apparatus, and computer-readable recording medium
A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis...
US-1,001,4071 Comparing twice-read memory cell data for error detection in a memory device
A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory...
US-1,001,4070 Data path integrity verification in memory devices
Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device...
US-1,001,4069 Memory device and refresh methods to alleviate the effects of row hammer condition
There may be provided a memory or memory system. A memory may include an active cell array comprising a plurality of unit cells coupled to a word line and...
US-1,001,4068 Semiconductor device
A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a...
US-1,001,4067 Semiconductor device and manufacturing method thereof
To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a...
US-1,001,4066 Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode...
US-1,001,4065 PPA (power performance area) efficient architecture for ROM (read only memory) and a ROM bitcell without a...
Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address...
US-1,001,4064 Non-volatile semiconductor storage device
According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier...
US-1,001,4063 Smart skip verify mode for programming a memory device
Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells....
US-1,001,4062 Apparatus and methods for determining a pass/fail condition of a memory device
Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank...
US-1,001,4061 Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in...
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory...
US-1,001,4060 Memory system and method for reducing read disturb errors
A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of...
US-1,001,4059 Memory controller, memory control method, and coefficient decision method
According to one embodiment, a distribution of threshold voltages of a plurality of memory cells is acquired from a nonvolatile memory which includes the...
US-1,001,4058 Semiconductor device and method of manufacturing the same
A semiconductor device may include an insulating layer, a bulk pattern, a stack structure, and a channel pattern. A first trench may be formed in the insulating...
US-1,001,4057 Devices including memory arrays, row decoder circuitries and column decoder circuitries
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data...
US-1,001,4056 Changing storage parameters
Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a...
US-1,001,4055 Split memory bank
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the...
US-1,001,4054 Semiconductor storage device
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell...
US-1,001,4053 Methods for backup sequence using three transistor memory cell devices
Methods for a backup sequence includes reading first data from a first data memory to a page buffer, copying the first data from the page buffer to a backup...
US-1,001,4052 Method, system and device for read signal generation
Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the...
US-1,001,4051 Data storage with data randomizer in multiple operating modes
Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and...
US-1,001,4050 High sum-rate write-once memory
Provided are modified one-hot (MOH) constructions for WOM codes with low encoding and decoding complexity, that achieve high sum-rates. Features include...
US-1,001,4049 Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on...
A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window...
US-1,001,4048 Dual interlocked storage cell (DICE) latch sharing active region with neighbor DICE latch and semiconductor...
A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.
US-1,001,4047 Memory module supporting time-division memory access
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory...
US-1,001,4046 Device, system, and method of memory allocation
Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random...
US-1,001,4045 Three-dimensional magnetic memory with multi-layer data storage layers
Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a...
US-1,001,4044 Semiconductor device, battery monitoring system, and address setting method of semiconductor device
A semiconductor device, which is daisy-chain connected with other semiconductor devices, includes a first communication section that receives reception data; a...
US-1,001,4043 Memory device having command window generator
A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay...
US-1,001,4042 Semiconductor device
A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency...
US-1,001,4041 Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed...
Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain,...
US-1,001,4039 Method and circuit for self-training of a reference voltage and memory system including the same
A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference...
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