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Patent # Description
US-1,001,3378 ASIC chip system dedicated for optical three-dimensional sensing
The present disclosure relates to a dedicated ASIC chip system for optical three-dimensional sensing, including a DEPTH ENGINE module, a REGISTER PROCESSOR...
US-1,001,3377 PCI express fabric routing for a fully-connected mesh topology
A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is...
US-1,001,3376 System including interface circuit for driving data transmission line to termination voltage
A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line...
US-1,001,3375 System-on-chip including asynchronous interface and driving method thereof
A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and...
US-1,001,3374 Bidirectional communication method between a master terminal and a slave terminal on a single transmission line
A bidirectional communication method between a master terminal and a slave terminal on a single transmission line includes the master terminal transmitting an...
US-1,001,3373 Multi-level message passing descriptor
In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller...
US-1,001,3372 Input/output apparatus and method
An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a...
US-1,001,3371 Configurable memory circuit system and method
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a...
US-1,001,3370 Method and system for providing access of a storage system using a shared storage module as a transport mechanism
According to one embodiment, a first control module (CM) of a storage system receives a first request from a client device to read first data stored in a second...
US-1,001,3369 Server system with BMC having hard disk drive monitoring function
A server system is disclosed. The server system comprises a host system, at least one hard disk (HD) drive, a host bus adapter (HBA), at least one indicator, a...
US-1,001,3368 Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for...
US-1,001,3367 I/O processing system including dynamic missing interrupt and input/output detection
An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing...
US-1,001,3366 Standardized hot-pluggable transceiving unit and method for controlling the unit through a web server function
The present disclosure relates to a standardized hot-pluggable transceiving unit executing a web server function for controlling the transceiving unit, and a...
US-1,001,3365 Method for programming a control unit of a motor vehicle
A method for programming a control unit of a motor vehicle, a previous program code executed in the control unit being stored in a memory area, a new program...
US-1,001,3364 Securing data using per tenant encryption keys
One embodiment is directed to a technique which secures data on a set of storage drives of a data storage system. The technique involves encrypting data from a...
US-1,001,3363 Encryption using entropy-based key derivation
A system may encrypt the contents of a memory using an encryption key that is generated based on an entropy-based key derivation function. The system may...
US-1,001,3362 Deterministic multifactor cache replacement
Some embodiments modify caching server operation to evict cached content based on a deterministic and multifactor modeling of the cached content. The modeling...
US-1,001,3361 Method to increase performance of non-contiguously written sectors
A method of managing data in a cache upon a cache write operation includes determining a number of non-contiguously written sectors on a track in the cache and...
US-1,001,3360 Managing reuse information with multiple translation stages
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least...
US-1,001,3359 Redundant disk array storage system and method using heterogeneous disks and a lookup table
A redundant disk array method includes allocating identically sized logical blocks of storage units together to form a stripe on each of several data storage...
US-1,001,3358 Computer system and memory allocation management method
A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource...
US-1,001,3357 Managing memory access requests with prefetch for streams
Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks...
US-1,001,3356 Facilitating prefetching for data streams with multiple strides
The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor...
US-1,001,3355 Cache management in a stream computing environment that uses a set of many-core hardware processors
Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by...
US-1,001,3354 Apparatus, system, and method for atomic storage operations
A storage layer (SL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata...
US-1,001,3353 Adaptive optimization of second level cache
Adaptive optimization of second level cache is disclosed. In an example embodiment, a system includes a database server and an enterprise application server,...
US-1,001,3352 Partner-aware virtual microsectoring for sectored cache architectures
Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at...
US-1,001,3351 Transactional execution processor having a co-processor accelerator, both sharing a higher level cache
A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding...
US-1,001,3350 Data storage device and operating method thereof
A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the...
US-1,001,3349 Memory controller, method thereof, and electronic devices having the memory controller
A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group...
US-1,001,3348 Parallel memory allocator employing liveness metrics
A liveness-based memory allocation module operating so that a program thread invoking the memory allocation module is provided with an allocation of memory...
US-1,001,3347 Non-blocking parallel memory mechanisms
A transaction descriptor associated with a vertical chain of row versions is received. The vertical chain of row versions is traversed. The vertical chain is...
US-1,001,3346 Method of decreasing write amplification of NAND flash using a journal approach
A journaling approach is used to distribute data of different sizes between areas of a segment's log on a physical NAND flash erase block. The Main area...
US-1,001,3345 Storage module and method for scheduling memory operations for peak-power management and balancing
A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains...
US-1,001,3344 Enhanced SSD caching
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or...
US-1,001,3343 Apparatus and method of refreshing a memory area of a non-volatile memory unit used in an embedded system
A method for performing a refresh of a first memory area of a non-volatile memory unit includes overwriting at least one additional memory area of the...
US-1,001,3342 Computing device, data transfer method between coprocessor and non-volatile memory, and computer-readable...
A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing...
US-1,001,3341 Semiconductor memory device having rank interleaving operation in memory module
A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The...
US-1,001,3340 Testing in virtualized computing environments
Technology is described for selecting parameter combinations corresponding to virtual instance configurations to be tested in a virtual computing environment...
US-1,001,3339 System and method for automating testing without scripting
A system and computer-implemented method for automating end-to end testing is provided. The system comprises a connection settings module to receive information...
US-1,001,3338 Techniques for automated software testing
Described are techniques for testing an application. A test script including one or more instructions is received to test an application. A user interaction...
US-1,001,3337 Feature switches for private cloud and on-premise application components
A set of features is received. A feature from the set of features includes a feature setting. The feature setting is adjusted based on a user input. A source...
US-1,001,3336 Information technology testing and testing data management
A testing and extract, transform and load (TETL) system is operable to interface with test platforms testing hardware or software components of information...
US-1,001,3335 Data flow analysis in processor trace logs using compiler-type information method and apparatus
A program control flow trace is obtained from a processor trace module, which may be hardware based, and is used, in combination with debug information and...
US-1,001,3334 Dynamic crash detection and debugging assistance
In an approach to identifying program bugs, one or more computer processor detect a first crash in a try block. The one or more computer processors determine a...
US-1,001,3333 Scalable continuous integration and delivery systems and methods
A scalable continuous integration (CI) system and/or method may be provided to manage and implement a plurality of code changes submitted in a code base. The...
US-1,001,3332 Monitoring mobile application performance
Aspects of the subject disclosure are directed towards monitoring application performance during actual use, particularly mobile application performance....
US-1,001,3331 Correlating queries issued by applications with their source lines and analyzing applications for problem...
Provided are techniques for invoking with a processor executing on a computer a source code parser to obtain source information that includes a first location...
US-1,001,3330 Automated mobile application verification
Disclosed are various embodiments for automatically testing and verifying applications. A user input profile is generated for an application by performing a...
US-1,001,3329 Dynamic tracing using ranking and rating
Method, computer program product, and system for dynamic tracing, including monitoring a log file, wherein the log file comprises events, wherein an event...
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