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Patent # Description
US-1,007,9194 Chip on film package
A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first...
US-1,007,9192 Semiconductor chip package assembly with improved heat dissipation performance
A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting...
US-1,007,9191 Heat spreader having thermal interface material retainment
In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC...
US-1,007,9190 Methods of fabricating an electronic package structure
A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a...
US-1,007,9189 P-type transparent conducting nickel oxide alloys
Disclosed herein is the formation of p-type transparent conducting oxides (TCO) having a structure of Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO. These...
US-1,007,9188 Resin composition for encapsulating, manufacturing method of on-vehicle electronic control unit, and on-vehicle...
Provided is a resin composition for encapsulating which is used for forming an encapsulating resin of an on-vehicle electronic control unit including a wiring...
US-1,007,9187 Semiconductor devices and methods for testing a gate insulation of a transistor structure
A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure...
US-1,007,9186 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate,...
US-1,007,9185 Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method...
A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first...
US-1,007,9184 Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
According to one embodiment, a semiconductor manufacturing apparatus includes a manufacturing processor, a signal acquisition unit, a frequency characteristic...
US-1,007,9183 Calculated electrical performance metrics for process monitoring and yield management
Methods and systems of process control and yield management for semiconductor device manufacturing based on predictions of final device performance are...
US-1,007,9182 Field effect transistor gate stack
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a...
US-1,007,9181 P-FET with strained silicon-germanium channel
A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region...
US-1,007,9180 Method of forming a semiconductor device
A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping...
US-1,007,9179 Wafer processing method
A wafer is divided into a plurality of individual devices along a plurality of division lines, the wafer being composed of a substrate and a functional layer...
US-1,007,9178 Formation method of semiconductor device structure using multilayer resist layer
Formation methods of a semiconductor device structure are provided. The method includes forming a bottom layer, a middle layer and an upper layer over a...
US-1,007,9177 Method for forming copper material over substrate
A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a ...
US-1,007,9176 Method of using a barrier-seed tool for forming fine pitched metal interconnects
A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the...
US-1,007,9175 Insulating a via in a semiconductor substrate
Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the...
US-1,007,9174 Composite contact plug structure and method of making same
An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer...
US-1,007,9173 Methods of forming metallization lines on integrated circuit products and the resulting products
One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate...
US-1,007,9172 Wiring structure and method of forming a wiring structure
A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure...
US-1,007,9171 Combined method for producing solids, involving laser treatment and temperature-induced stresses to generate...
The present invention relates to a method for the production of at least one three-dimensional layer of solid material, in particular for usage as wafer, and/or...
US-1,007,9170 High resistivity SOI wafers and a method of manufacturing thereof
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an...
US-1,007,9169 Backside stealth dicing through tape followed by front side laser ablation dicing process
A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on...
US-1,007,9168 Ceramic electrostatic chuck including embedded Faraday cage for RF delivery and associated methods for...
A ceramic assembly is attached to a lower support structure having a bowl shape. The ceramic assembly has a top surface configured to support a substrate. At...
US-1,007,9167 Electrostatic chucking device
Provided is an electrostatic chucking device having high heat resistance. The electrostatic chucking device of the present invention includes a first ceramic...
US-1,007,9166 Processing apparatus
A temporary receiving unit of a processing apparatus includes a first support rail having a first bottom wall and a first side wall for guiding a workpiece for...
US-1,007,9165 Electrostatic chuck with independent zone cooling and reduced crosstalk
An electrostatic chuck is described with independent zone cooling that leads to reduced crosstalk. In one example, the chuck includes a puck to carry a...
US-1,007,9164 System, apparatus, and method for processing substrates using acoustic energy
A system, apparatus, and method for processing substrates using acoustic energy. In one aspect, the invention can be a system for processing flat articles...
US-1,007,9163 Unit for supplying treatment liquid and apparatus for treating substrate
Disclosed is an apparatus for treating a substrate. The apparatus includes a support unit that supports the substrate, and a treatment liquid supply unit that...
US-1,007,9162 Method for making lead frames for integrated circuit packages
Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed...
US-1,007,9161 Method for producing a semiconductor package
An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily...
US-1,007,9160 Surface mount package for semiconductor devices with embedded heat spreaders
A method of mounting one or more semiconductor or microelectronic chips, which includes providing a carrier; temporarily adhering the one or more semiconductor...
US-1,007,9159 Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP)...
Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP)...
US-1,007,9158 Vertical trench routing in a substrate
An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a...
US-1,007,9157 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this...
US-1,007,9156 Semiconductor package including dielectric layers defining via holes extending to component pads
The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component...
US-1,007,9155 Semiconductor device manufacturing method
A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which...
US-1,007,9154 Atomic layer etching of silicon nitride
A method for selectively etching SiN with respect to SiO or SiGe or Si of a structure is provided comprising providing a plurality of cycles of atomic layer...
US-1,007,9153 Semiconductor storage device
In a substrate processing method according to the embodiment, a first material is implanted into a surface of a target film to modify the surface of the target...
US-1,007,9152 Method for forming planarized etch mask structures over existing topography
A method used to create small pattern features over existing topography variations. The method includes providing a substrate having a surface having non-planar...
US-1,007,9151 Method for bottom-up deposition of a film in a recessed feature
Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method...
US-1,007,9150 Method and apparatus for dry gas phase chemically etching a structure
According to the invention there is provided a method of dry gas phase chemically etching a structure comprising the steps of: positioning the structure in an...
US-1,007,9149 Semiconductor device with self-aligned carbon nanotube gate
A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is...
US-1,007,9148 Material removal process for self-aligned contacts
A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that...
US-1,007,9147 Method of forming interconnects for semiconductor devices
A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate,...
US-1,007,9146 Resist underlayer film forming composition containing silicon containing cyclic organic group having hetero atom
A resist underlayer film composition for lithography, including: a silane: at least one among a hydrolyzable organosilane, a hydrolysis product thereof, and a...
US-1,007,9145 Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method
The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method...
US-1,007,9144 Composition for layered transition metal chalcogenide compound layer and method of forming layered transition...
Provided are a composition for forming a layered transition metal chalcogenide compound layer and a method of forming a layered transition metal chalcogenide...
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