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Patent # Description
US-1,009,0431 System and method for thin film photovoltaic modules and back contact for thin solar cells
The present disclosure provides improved thin film photovoltaic devices and related methods of fabrication. More particularly, the present disclosure provides...
US-1,009,0430 System for manufacturing a shingled solar cell module
A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which...
US-1,009,0429 Integrated on chip detector and zero waveguide module structure for use in DNA sequencing
A semiconductor structure for use in single molecule real time DNA sequencing technology is provided. The structure includes a semiconductor substrate including...
US-1,009,0428 Solar cell and method for manufacturing the same
A solar cell and a method for manufacturing the same are disclosed. The solar cell may include a substrate, an emitter layer positioned at a first surface of...
US-1,009,0427 Package structure of long-distance sensor and packaging method of the same
A package structure of a long-distance sensor includes a substrate, a light-emitting chip, a sensing chip, two packaging gel bodies, a cap, and two sheltering...
US-1,009,0426 Dark current mitigation with diffusion control
A photosensor device for reducing dark current is disclosed. The photosensor device includes a photon absorbing layer and two or more photosensor diffusions in...
US-1,009,0424 Roll-to-roll solution process method for fabricating CIGS solar cells and system for the same
A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The...
US-1,009,0423 Polymer containing 1,2,5-benzoselenadiazole-N-R1-5,6-dicarboxylic acid imide and preparation method and use thereof
The present invention discloses a polymer containing 1,2,5-benzoselenadiazole-N--R.sub.1-5,6-dicarboxylic acid imide, and a preparation method and use thereof....
US-1,009,0422 Integrated photodetector waveguide structure with alignment tolerance
An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a...
US-1,009,0421 Foil-based metallization of solar cells
Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A...
US-1,009,0420 Via etch method for back contact multijunction solar cells
This disclosure relates to semiconductor devices and methods for fabricating semiconductor devices. Particularly, the disclosure relates to back-contact-only...
US-1,009,0419 Solar cell and method for manufacturing the same
A solar cell includes a substrate formed of n-type single crystal silicon, an emitter region of a p-type which is positioned at a first surface of the substrate...
US-1,009,0418 Solar battery module
A solar battery module according to one embodiment comprises: a support substrate having a through-hole formed therein; a plurality of solar battery cells...
US-1,009,0417 Silicon carbide semiconductor device and fabrication method of silicon carbide semiconductor device
A p-type region, a p.sup.- type region, and a p.sup.+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type...
US-1,009,0415 Thin film transistors with epitaxial source/drain contact regions
A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first...
US-1,009,0414 TFT substrate manufacture method
The present invention provides a TFT (Thin Film Transistor) substrate manufacture method, which includes forming a TFT gate electrode on a substrate,...
US-1,009,0413 Semiconductor device and method of fabricating the same
A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active...
US-1,009,0412 Vertical transistor with back bias and reduced parasitic capacitance
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the...
US-1,009,0411 Air-gap top spacer and self-aligned metal gate for vertical fets
A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. A top...
US-1,009,0410 Forming a combination of long channel devices and vertical transport fin field effect transistors on the same...
A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a...
US-1,009,0409 Method for fabricating LDMOS with self-aligned body
A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an...
US-1,009,0408 Semiconductor device and method of manufacturing semiconductor device
A SJ-MOSFET includes a parallel pn layer in which an n-type drift region and a p-type partition region are alternately arranged repeatedly along a direction...
US-1,009,0407 Semiconductor device and manufacturing method
To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor...
US-1,009,0406 Non-planar normally off compound semiconductor device
A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride...
US-1,009,0405 Semiconductor device having group III-V material active region and graded gate dielectric
Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an...
US-1,009,0404 Semiconductor device including emitter regions and method of manufacturing the semiconductor device
A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is...
US-1,009,0403 Power semiconductor device with semiconductor pillars
A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and...
US-1,009,0402 Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first...
US-1,009,0401 Thin film transistor, manufacturing method thereof, and display device including the same
A thin film transistor includes a substrate, a semiconductor layer, a first insulating layer, and a gate electrode. The gate electrode overlaps the...
US-1,009,0400 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-1,009,0399 Semiconductor device and a manufacturing method thereof
The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has...
US-1,009,0398 Manufacturing method of patterned structure of semiconductor
A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon;...
US-1,009,0397 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack positioned over the...
US-1,009,0396 Method for fabricating metal gate devices and resulting structures
A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer...
US-1,009,0395 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
US-1,009,0394 Ohmic contact structure for group III nitride semiconductor device having improved surface morphology and...
Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic...
US-1,009,0393 Method for forming a field effect transistor device having an electrical contact
A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a...
US-1,009,0392 Semiconductor device and manufacturing method thereof
A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device...
US-1,009,0391 Tunable breakdown voltage RF FET devices
A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an...
US-1,009,0390 FinFET with trench field plate
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second...
US-1,009,0389 Semiconductor memory device and fabrication method thereof
A semiconductor memory device and a method of fabrication of the same are provided. The semiconductor memory device comprises a two-terminal memory cell...
US-1,009,0388 Crystalline multilayer structure and semiconductor device
Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a...
US-1,009,0387 Electronic device with a reverse biased HEMT transistor
An electronic device having at least a first HEMT transistor and bias circuit able to at least reverse bias the first HEMT transistor by applying an electric...
US-1,009,0386 Graphene-metal bonding structure, method of manufacturing the same, and semiconductor device having the...
Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the...
US-1,009,0385 Methods of forming a vertical transistor device with a channel structure comprised of alternative semiconductor...
One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a...
US-1,009,0384 Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer
A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A...
US-1,009,0383 Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced...
US-1,009,0382 Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same
The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An...
US-1,009,0381 Semiconductor device including air-gap
A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of...
US-1,009,0380 Semiconductor device having localized charge balance structure and method
In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then...
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