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Patent # Description
US-1,009,0328 Semiconductor device
A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second...
US-1,009,0327 Semiconductor device and method for forming the same
Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed...
US-1,009,0326 Flexible display substrate and a manufacturing method thereof, as well as a flexible display device
The embodiments of the present invention provide a flexible display substrate and a manufacturing method thereof, as well as a flexible display device, which...
US-1,009,0325 Circuit cells having separated gate electrodes
A device includes first circuit cells. Each of the first circuit cells includes isolation transistors, a first type transistor, a second type transistor, and a...
US-1,009,0324 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-1,009,0323 Semiconductor device including dielectric layer
A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes...
US-1,009,0322 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film,...
US-1,009,0321 Integrated circuit device and method for manufacturing same
An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an...
US-1,009,0320 Semiconductor device and method for manufacturing the same
A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a...
US-1,009,0319 Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar...
US-1,009,0318 Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a...
A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating...
US-1,009,0317 Methods and apparatuses having memory cells including a monolithic semiconductor channel
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of...
US-1,009,0316 3D stacked multilayer semiconductor memory using doped select transistor channel
In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped...
US-1,009,0315 Semiconductor memory device in which an array chip including three-dimensionally disposed memory cells bonded...
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected...
US-1,009,0314 Vertical memory devices and methods of manufacturing the same
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of...
US-1,009,0313 NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch....
US-1,009,0312 Semiconductor memory device
According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality...
US-1,009,0311 Cost-free MTP memory structure with reduced terminal voltages
Device and methods for forming a single transistor non-volatile (NV) multi-time programmable (MTP) memory cell are disclosed. The disclosed memory cell is...
US-1,009,0310 Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region...
US-1,009,0309 Nonvolatile memory cell capable of improving program performance
A non-volatile memory cell is disclosed. A select gate transistor, a following gate transistor, and an antifuse varactor are coupled in series on an active...
US-1,009,0308 Semiconductor memory device
A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type...
US-1,009,0307 Decoupling capacitor on strain relaxation buffer layer
An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second...
US-1,009,0306 Fin-FET devices and fabrication methods thereof
A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a...
US-1,009,0305 Fin field effect transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits employing...
Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased...
US-1,009,0304 Isolation well doping with solid-state diffusion sources for FinFET architectures
An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that...
US-1,009,0303 Fabrication of vertical field effect transistors with uniform structural profiles
Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods...
US-1,009,0302 Self-aligned shallow trench isolation and doping for vertical fin transistors
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off...
US-1,009,0301 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-1,009,0300 Fin-like field effect transistor (FinFET) device and method of manufacturing same
A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin...
US-1,009,0299 MOSFET transistors with robust subthreshold operations
An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region...
US-1,009,0298 Integrated packaging structure
An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first...
US-1,009,0297 Semiconductor device
A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n.sup.+ emitter region and...
US-1,009,0296 Semiconductor device, manufacturing method thereof, and electronic apparatus
A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by...
US-1,009,0295 Biased transistor module
A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a...
US-1,009,0294 Semiconductor device
A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall...
US-1,009,0293 Integrated device with P-I-N diodes and vertical field effect transistors
An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second...
US-1,009,0292 Radial nanowire Esaki diode devices and methods
A radial nanowire Esaki diode device includes a semiconductor core of a first conductivity type and a semiconductor shell of a second conductivity type...
US-1,009,0291 Electrostatic discharge protection semiconductor device and layout structure of ESD protection semiconductor device
A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped...
US-1,009,0290 Stacked electrostatic discharge diode structures
An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render...
US-1,009,0289 Integrated circuits with standard cell
The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line...
US-1,009,0288 Semiconductor device and semiconductor system
A semiconductor system includes a first semiconductor device suitable for outputting an external command and a termination control signal and being inputted...
US-1,009,0287 Deep high capacity capacitor for bulk substrates
A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon...
US-1,009,0286 Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
US-1,009,0285 Light emitting module
To provide a light emitting module capable of reducing luminance unevenness. A light emitting module 10 includes an element substrate 11 extending in one...
US-1,009,0284 Semiconductor device and method of manufacture
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and...
US-1,009,0283 Methods and systems for improving power delivery and signaling in stacked semiconductor devices
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the...
US-1,009,0282 Semiconductor device assemblies with lids including circuit elements
A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a...
US-1,009,0281 Method and device for controlling operation using temperature deviation in multi-chip package
A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n)...
US-1,009,0280 Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies...
A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up...
US-1,009,0279 Stray inductance reduction in packaged semiconductor devices and modules
In a general aspect, an apparatus can include a first substrate operatively coupled with a second substrate. The apparatus can also include a power supply...
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