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Patent # Description
US-1,009,0278 Semiconductor packages
A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second...
US-1,009,0277 3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package...
US-1,009,0276 Semiconductor package to reduce warping
A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor...
US-1,009,0275 Bonding method using bonding material
A method of bonding two different substances includes the steps of: applying a bonding material containing a flux component that includes an organic material...
US-1,009,0274 Flip chip interconnection with reduced current density
A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the...
US-1,009,0273 Apparatus and method for manufacturing semiconductor device
A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit...
US-1,009,0272 Chip package and chip packaging method
According to an embodiment of the present disclosure, a chip package including at least one chip, a first encapsulation layer, a redistribution layer, and a...
US-1,009,0271 Metal pad modification
The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of...
US-1,009,0270 Metal pillar with cushioned tip
A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal...
US-1,009,0269 Bump structure, display device including a bump structure, and method of manufacturing a bump structure
A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first...
US-1,009,0268 Method of forming solder bump, and solder bump
A solder bump formed on an Ni electrode with the use of a solder ball containing Bi as a main component and Sn as a sub component. The solder ball contains Sn...
US-1,009,0267 Bump structure and method for forming the same
A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor...
US-1,009,0266 Semiconductor device, and method of fabricating the same
A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip...
US-1,009,0265 Semiconductor device with metal structure electrically connected to a conductive structure
A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure...
US-1,009,0264 Method to improve CMP scratch resistance for non planar surfaces
A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate,...
US-1,009,0263 Semiconductor package, printed circuit board substrate and semiconductor device
A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer...
US-1,009,0262 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-1,009,0261 Microelectronic package debug access ports and methods of fabricating the same
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
US-1,009,0260 Semiconductor apparatus with fake functionality
A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on...
US-1,009,0259 Non-rectangular electronic device components
Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a...
US-1,009,0258 Crack-stop structure for an IC product and methods of making such a crack-stop structure
One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a...
US-1,009,0257 Electrical package including bimetal lid
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads...
US-1,009,0256 Semiconductor structure
A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a...
US-1,009,0255 Dicing channels for glass interposers
The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and...
US-1,009,0254 Wafer alignment methods in die sawing process
A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface...
US-1,009,0253 Semiconductor package
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an...
US-1,009,0252 Package-on-package type semiconductor device including fan-out memory package
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over...
US-1,009,0251 Semiconductor chip having a dense arrangement of contact terminals
A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and...
US-1,009,0250 Memory structure and method for manufacturing the same
A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The...
US-1,009,0249 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a...
US-1,009,0248 Conductive structure and manufacturing method thereof, and electronic device and manufacturing method thereof
An opening is formed in an insulating film being a formation site, vertical and parallel CNTs are formed, tip portions of the CNTs are inserted into the...
US-1,009,0247 Semiconductor device formed by wet etch removal of Ru selective to other metals
A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and...
US-1,009,0246 Metal interconnect structure and fabrication method thereof
The present disclosure provides metal interconnect structures and fabrication methods thereof. An exemplary fabrication method of the metal interconnect...
US-1,009,0245 Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first...
US-1,009,0244 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that...
US-1,009,0243 Inductor for semiconductor integrated circuit
An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive...
US-1,009,0242 Etch stop layer in integrated circuits
An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride...
US-1,009,0241 Device, package structure and method of forming the same
Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside...
US-1,009,0240 Interconnect structure with capacitor element and related methods
Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming...
US-1,009,0239 Metal-insulator-metal on-die capacitor with partial vias
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die....
US-1,009,0238 Wiring substrate and method for manufacturing the same
A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is...
US-1,009,0237 Semiconductor device and manufacturing method thereof
A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the...
US-1,009,0236 Interposer having a pattern of sites for mounting chiplets
The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site...
US-1,009,0235 Semiconductor device and semiconductor package
According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board...
US-1,009,0234 Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of...
US-1,009,0233 Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second...
US-1,009,0232 Bumpless fan-out chip stacking structure and method for fabricating the same
A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a...
US-1,009,0231 Conductive connections, structures with such connections, and methods of manufacture
A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by...
US-1,009,0230 Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate
A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom...
US-1,009,0229 Semiconductor device and method for manufacturing the same
A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the...
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