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Patent # Description
US-1,008,9273 Dynamic addressing
This invention relates to a dynamically addressable master-slave system and a method for dynamic addressing of slave units, wherein a master unit and a...
US-1,008,9272 Data-category switch module in the control plane for use with internet of things devices
An information handling system containing a data-category switch module operating in the control plane for the exchange of data between internet of things...
US-1,008,9271 Field bus system
A field bus system includes at least one bus module designed as a master module with at least one connecting device for connection to a network and with at...
US-1,008,9270 Interchangeable power and signal contacts for IO connectors
Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a...
US-1,008,9269 Mobile device, engineering tool device, system and methods for cable configuration in a process control system
A mobile device for determining cable connections between field devices and I/O modules in a process control system, wherein the mobile device includes a cable...
US-1,008,9268 Network subscriber
A network subscriber comprises a plurality of individual functional units, each individual functional unit comprising an application interface. The network...
US-1,008,9267 Low latency efficient sharing of resources in multi-server ecosystems
A method is provided in one example embodiment and includes receiving by a network element a request from a network device connected to the network element to...
US-1,008,9266 Power saving feature for storage subsystems
Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining...
US-1,008,9265 Methods and systems for handling interrupt requests
Systems, methods, and computer readable medium are provided that improve the management of interrupt requests in multiple processor computer systems. Interrupt...
US-1,008,9264 Callback interrupt handling for multi-threaded applications in computing environments
A mechanism is described for facilitating callback interrupt handling for multi-threaded applications in computing environments. A method of embodiments, as...
US-1,008,9263 Synchronization of interrupt processing to reduce power consumption
A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first...
US-1,008,9262 Reduced overhead safepoint mechanism using signals
A system and method for searching for and finding data across industrial time-series data is disclosed executing a series of instructions on a computer system....
US-1,008,9261 Discriminating dynamic connection of disconnectable peripherals
An enterprise wide data processing system includes at least one watchdog unit and/or software service that is configured to automatically detect an attempt to...
US-1,008,9260 Control method and system for accessing data among different electronic devices
A system for accessing data among at least two different electronic devices is provided. The system includes a demanding electronic device and a providing...
US-1,008,9259 Precise, efficient, and transparent transfer of execution between an auto-generated in-line accelerator and...
A data processing system is disclosed that includes an in-line accelerator and a processor. The system can be extended to include an in-line accelerator and...
US-1,008,9258 Semiconductor integrated circuit, and data interface system provided with same, which provides for dynamic...
A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory....
US-1,008,9257 Semiconductor storage device and control method thereof
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips...
US-1,008,9256 Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling
A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first...
US-1,008,9255 High performance host queue monitor for PCIE SSD controller
Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue...
US-1,008,9254 Methods and apparatus for dynamically selecting an instruction set
Methods and apparatus for dynamic instruction set selection for producing an output parameter based on one or more available input parameters are presented. In...
US-1,008,9253 Data store for a modular assembly system
A data store for a modular assembly system is described. The data store comprises a number of records, each record relating to a physical module in the modular...
US-1,008,9252 USB communication control method for USB accessory
A USB communication control method, in which a USB host and a USB accessory executing an Android operating system are connected to each other through a USB...
US-1,008,9251 Multi-modal active cable for performing a mode identification operation
A system and method for providing a multi-modal active cable. In certain embodiments, the multi-modal active cable enables transmission of alternative display...
US-1,008,9250 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-1,008,9249 In-package storing of data for an electronic device
An apparatus, shipping container, and system for in-package storing of data for an electronic device are disclosed. In one example, the apparatus comprises an...
US-1,008,9248 Hacking-resistant computer design
A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal...
US-1,008,9247 System and method for coupling a host device to secure and non-secure devices
One embodiment provides an apparatus. The apparatus includes an input output memory management unit (I/O MMU), a non-secure operating system (OS) driver, a...
US-1,008,9246 Access files
Data security access and management may require a server dedicated to monitoring document access requests and enforcing rules and policies to limit access to...
US-1,008,9245 Management of encryption keys for multi-mode network storage device
One method for managing encryption includes identifying an available or a secure mode. During restarts a passphrase must be entered in secure mode but not in...
US-1,008,9244 Hardware for miss handling from a translation protection data structure
A processor includes a memory to store original code and a fingerprint data structure, which stores, in a way thereof, an entry including a physical address for...
US-1,008,9243 Memory controller and system including variable address mapping tables and a fixed address mapping table
A memory controller includes a plurality of ports coupled with a host device and a plurality of channels coupled with a memory device. The memory controller...
US-1,008,9242 Memory management for a hierarchical memory system
Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual...
US-1,008,9241 Memory system
According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is...
US-1,008,9240 Cache accessed using virtual addresses
A computer architecture provides a memory cache that is accessed not by physical addresses but by virtual addresses directly from running processes. Ambiguities...
US-1,008,9239 Memory system architecture
Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU....
US-1,008,9238 Method and apparatus for a shared cache with dynamic partitioning
Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache...
US-1,008,9237 Data filter cache designs for enhancing energy efficiency and performance in computing systems
Certain embodiments herein relate to, among other things, designing data cache systems to enhance energy efficiency and performance of computing systems. A data...
US-1,008,9236 Apparatus and method of performing agentless remote IO catching analysis, prediction, automation, and...
A host device includes a controller configured to receive input/output (IO) access information associated with an IO workload, the IO access information...
US-1,008,9235 Dynamic trim processing with disk caching
Systems and methods for handling operation requests in a computing device. The methods comprise: queuing a first I/O operation and first TRIM operation in a...
US-1,008,9234 Disk cache allocation
Implementations disclosed herein provide a method comprising determining a workload on a disk cache with a storage device controller, determining a state of a...
US-1,008,9233 Method of partitioning a set-associative cache in a computing platform
A method of partitioning a set-associative cache for a plurality of software components may comprise identifying a cache height equal to a number of sets in the...
US-1,008,9232 Mode switching for increased off-chip bandwidth
Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a...
US-1,008,9231 Filtering of redundently scheduled write passes
Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from...
US-1,008,9230 Resource-specific flushes and invalidations of cache and memory fabric structures
Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first...
US-1,008,9229 Cache allocation with code and data prioritization
Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to...
US-1,008,9228 I/O blender countermeasures
A cache storage method includes providing a storage cache cluster, comprising a plurality of cache storage elements, for caching I/O operations from a plurality...
US-1,008,9227 Systems, devices and methods using a solid state device as a caching medium with a write cache flushing algorithm
A method for performing cache flushing operations in a data storage system can include maintaining a plurality of SSDs as a cache medium for a data storage...
US-1,008,9226 Systems and methods for immediate physical erasure of data stored in a memory system in response to a user command
Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory...
US-1,008,9225 Improving garbage collection efficiency by reducing page table lookups
A flash memory control technology with high efficiency, which records a logical page table in a random access memory. The logical pages that have been collected...
US-1,008,9224 Write caching using volatile shadow memory
An apparatus is provided that includes a non-volatile (device storage) memory configured to store data in a plurality of locations. The apparatus also includes...
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