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Patent # Description
US-1,009,7210 Parallel bit interleaver
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword...
US-1,009,7209 Interleaving and mapping method and deinterleaving and demapping method for LDPC codeword
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises:...
US-1,009,7208 Error locator polynomial decoder method
A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter....
US-1,009,7207 ECC circuit, storage device and memory system
A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2.sup.m-1) bits at maximum which is...
US-1,009,7206 Method and apparatus for performing encoding using block code having input/output of variable length
There are provided an encoding method and an encoder performing an encoding by an operation of generating a first output message by encoding an input message...
US-1,009,7205 Transmission device, reception device, transmission method, and reception method for suppressing the degrading...
In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external...
US-1,009,7204 Low-density parity-check codes for WiFi networks
A system includes a code rate selecting module and a matrix generating module. The code rate selecting module is configured to select a code rate of k/n to...
US-1,009,7203 Lane-striped computation of packet CRC to maintain burst error properties
A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the...
US-1,009,7202 SSD compression aware
Embodiments of the present invention include a compression system including one or more compressibility inputs; a compression predictor configured to predict...
US-1,009,7201 LZ77 compression of data with data runs
Methods and apparatus are described by for compressing data using LZ77 compression. Embodiments determine an initial run from input data. The initial run...
US-1,009,7200 Resynchronization of sample rate converters
A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by...
US-1,009,7199 Digital to analog converter with remote cascode devices
A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC...
US-1,009,7198 SAR ADC
Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a capacitor-resistor hybrid digital-to-analog...
US-1,009,7196 Image element, processing method, and electronic device
The present technology relates to an imaging element, a processing method, and an electronic device which are capable of reducing deterioration in an image...
US-1,009,7195 Digital-to-analog converter (DAC) with enhanced dynamic element matching (DEM) and calibration
Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based...
US-1,009,7194 Method of synthesis of an analogue noise, noise synthesizer and coding chain using such a synthesiser
A method comprises at least the following steps: generating pseudo random noise in the digital domain coded on a number N of bits, sampled at a given frequency...
US-1,009,7193 Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a...
US-1,009,7192 Circuits for current recycling and related methods
Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance...
US-1,009,7191 Atomic oscillator
An atomic oscillator includes a gas cell having alkali metal atoms sealed therein; alight source that irradiates the gas cell with light; and a light detecting...
US-1,009,7190 Wide capture range reference-less frequency detector
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control...
US-1,009,7189 Semiconductor device
A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control...
US-1,009,7188 System, method and apparatus for phase hits and microphonics cancellation
A system and method for system, method and apparatus for phase hits and microphonics cancellation. In addition to a first RF synthesizer source, a device also...
US-1,009,7187 Digital synthesizer, radar device and method therefor
A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired...
US-1,009,7186 Robust tunable coupling between superconductive circuits
Systems and methods are provided for linking two components in a superconducting circuit. A plurality of circuit elements, each comprising one of an inductor, a...
US-1,009,7185 System level interconnect with programmable switching
In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The...
US-1,009,7184 Differential receiver
One example discloses A differential receiver, including: a set of high voltage differential inputs configured to receive a first range of differential...
US-1,009,7183 Level shifter and method of calibration
A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the...
US-1,009,7182 Integrated circuit layout wiring for multi-core chips
An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a...
US-1,009,7181 Apparatus and method for standby current control of signal path
Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second...
US-1,009,7180 Reinforced key assembly
Embodiments are directed to a dome switch and methods related to the use thereto. In one aspect, an embodiment includes a key cap. The embodiment may further...
US-1,009,7179 Mixing module and capacitive touch panel
A mixing module (40) comprises a switching mixer (400), controlled by a switch signal and configured to receive an inputting signal and generate an outputting...
US-1,009,7178 Isolated bidirectional high-voltage analog switch
Embodiments of the present disclosure include a bidirectional analog switch having a pair of high-voltage transistors coupled together via a common source and...
US-1,009,7177 Switch device, control method of the same, and control method of transfer switch system using the same
A switch device includes first and second switch units that are coupled respectively to first and second output terminals. Each of the first and second switch...
US-1,009,7176 Driving device for switching element and power conversion system
In a driving device, a resistor is provided on a current path connected to an on-off control terminal of a switching element. The current path permits a drive...
US-1,009,7175 Semiconductor device and DC-DC converter
According to an embodiment, a semiconductor device includes: a first modulation circuit configured to generate a reference signal based on a first clock signal;...
US-1,009,7174 Semiconductor device
A semiconductor device includes a switching element including a control electrode, a first main electrode, and a second main electrode: a gate driver connected...
US-1,009,7173 Switch control device and method for power
A switch control device includes a switch device and a control device. The switch device includes first and second input terminals, an output terminal, a...
US-1,009,7172 Method for protecting a controllable semiconductor switch from overload and short-circuiting in a load circuit
A method for protecting a controllable semiconductor switch from overload and short-circuiting in a load circuit, the method--including detecting an output...
US-1,009,7171 Radio frequency switch with low oxide stress
A RF switch circuit includes a voltage divider circuit and a semiconductor device. The semiconductor device has an activated state and a deactivated state. The...
US-1,009,7170 Circuit and method for low power chip enable circuitry
A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a...
US-1,009,7169 Method and apparatus for reducing impact of transistor random mismatch in circuits
An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node,...
US-1,009,7168 Current-mode clock distribution
Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to...
US-1,009,7167 Semiconductor device
To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory...
US-1,009,7166 Transformer coupled control isolation for direct current control signals
A switch drive and control arrangement may comprise a first transformer configured to receive a control signal, a second transformer configured to receive a...
US-1,009,7165 High gamma compact harmonic tuner
Compact, high Gamma, wideband, multi-carriage-multi-harmonic tuners use a meandering slabline structure and multiple probes and carriages. The meandering...
US-1,009,7164 Monolithic attenuator, limiter, and linearizer circuits using non-linear resistors
Monolithic attenuator, limiter, and linearizer circuitry to be integrated with other circuitry on a chip are provided. According to one aspect, a monolithic...
US-1,009,7163 Low order filter circuit having frequency correction function, frequency correction method for the low order...
A low order filter circuit having a frequency correction function, a frequency correction method for a low order filter circuit, and a high order filter circuit...
US-1,009,7162 Wireless charger receiver-side communication interference elimination
Embodiments of an apparatus are disclosed. In an embodiment, a power receiver unit is disclosed. The power receiver unit includes a power pick-up unit, a...
US-1,009,7161 Compensation circuit for acoustic resonators
In one embodiment, filter circuitry includes a series acoustic resonator between first and second nodes. A main series resonance is provided between the first...
US-1,009,7160 Ladder-type filter, duplexer, and module
A ladder-type filter includes: one or more series resonators connected in series between an input terminal and an output terminal; two or more parallel...
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