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Patent # Description
US-1,009,6708 Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate
An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is...
US-1,009,6707 Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for...
The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples...
US-1,009,6706 Vertical device architecture
In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source...
US-1,009,6705 Integrated high side gate driver structure and circuit for driving high side power transistors
An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity...
US-1,009,6704 Semiconductor device having a non-depletable doping region
A semiconductor device includes a plurality of compensation regions of a vertical electrical element arrangement, a plurality of drift regions of the vertical...
US-1,009,6703 Semiconductor device and method of manufacturing semiconductor device
A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n.sup.--type silicon carbide layer is...
US-1,009,6702 Multi-step surface passivation structures and methods for fabricating same
A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the...
US-1,009,6701 Gallium nitride materials and methods associated with the same
Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures...
US-1,009,6700 Power semiconductor device comprising trench structures
A power semiconductor device includes a semiconductor substrate, trench structures comprising a first, a second, a third and a fourth trench structure formed in...
US-1,009,6699 Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor
A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and...
US-1,009,6698 Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin...
US-1,009,6697 III-V FIN generation by lateral growth on silicon sidewall
A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a...
US-1,009,6696 Field effect transistors having a fin
An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the...
US-1,009,6695 Closely packed vertical transistors with reduced contact resistance
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a...
US-1,009,6694 Process for fabricating a vertical-channel nanolayer transistor
A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of...
US-1,009,6693 Method for manufacturing semiconductor structure with multi spacers
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a...
US-1,009,6692 Vertical field effect transistor with reduced parasitic capacitance
Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on...
US-1,009,6691 Methods for forming metal silicide
A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides...
US-1,009,6690 Circuit structure, transistor and semiconductor device
A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a Al.sub.xGa.sub.(1-X)N (AlGaN) layer over the III-V semiconductor...
US-1,009,6689 Low end parasitic capacitance FinFET
Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with...
US-1,009,6688 Integrated circuit device and method of manufacturing the same
An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in...
US-1,009,6687 Semiconductor device and method of fabricating the same
Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first...
US-1,009,6686 Thin film transistor, fabrication method thereof, repair method thereof and array substrate
Embodiments of the present disclosure disclose a thin film transistor, a fabrication method thereof, a repair method thereof, and an array substrate. The thin...
US-1,009,6685 Drift region implant self-aligned to field relief oxide with sidewall dielectric
An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region....
US-1,009,6684 Metal oxide film and semiconductor device
A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a...
US-1,009,6683 Group III-N transistor on nanoscale template structures
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall....
US-1,009,6682 III-N devices in Si trenches
A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material...
US-1,009,6681 Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells
The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter...
US-1,009,6680 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film...
US-1,009,6679 Approach to preventing atomic diffusion and preserving electrical conduction using two dimensional crystals and...
A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the...
US-1,009,6678 Methods for coating semiconductor nanocrystals
A coated quantum dot and methods of making coated quantum dots are provided.
US-1,009,6677 Methods for forming a semiconductor device and a semiconductor device
A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises...
US-1,009,6676 Semiconductor device and manufacturing method thereof
A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on...
US-1,009,6675 Spasers to speed up CMOS processors
A processor includes a transistor pair of a first transistor and a second transistor. The first transistor of the transistor pair is coupled to a Spaser and...
US-1,009,6674 Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)
A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a...
US-1,009,6673 Nanowire with sacrificial top wire
Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial...
US-1,009,6672 Semiconductor device having barrier layer to prevent impurity diffusion
A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate...
US-1,009,6671 Organic light emitting display device and method for manufacturing same
An organic light emitting device includes a base substrate having a pixel region and a non-pixel region, an organic light emitting element on the pixel region,...
US-1,009,6670 Semiconductor unit, method of manufacturing the same, and electronic apparatus
There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the...
US-1,009,6669 Display device
One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential...
US-1,009,6668 Display device including an organic layer having an uneven surface with a plurality of protrusions in a bending...
A display device includes: a substrate including a bending area located between a first region and a second region; an organic layer disposed over the...
US-1,009,6667 Display device
A display device includes a substrate including a display area and a non-display area disposed at a peripheral area of the display area. A plurality of pixels...
US-1,009,6666 Display apparatus, manufacturing method of display apparatus, and electronic device
A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display...
US-1,009,6665 Electro-optical device, electronic apparatus, and method of driving electro-optical device
A second data transfer line that is coupled to a gate layer of a drive transistor is formed in a layer higher than the gate layer, and a transfer capacitor is...
US-1,009,6664 Flexible organic light emitting display manufacturing method
A method for manufacturing a flexible organic light emitting display is disclosed. The method is: sequentially forming a first buffer layer, a switch array...
US-1,009,6663 Manufacturing method of array substrate, array substrate and display device
A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises:...
US-1,009,6662 Organic light emitting display device including a tandem structure and method of manufacturing the organic...
An organic light emitting display (OLED) device includes a substrate including a light emitting region and a peripheral region. An auxiliary power supply wire...
US-1,009,6661 Display device
A display device includes: a display panel including a display area for displaying an image; a window provided on an upper portion of the display panel; a...
US-1,009,6660 Array substrate, method for manufacturing array substrate, and display device
The present disclosure relates to an array substrate, a method for manufacturing the array substrate and a display device. The array substrate may include a...
US-1,009,6659 Top emission type organic light emitting diode display device
The present disclosure includes a top emission type organic light emitting diode display device. The top emission type organic light emitting diode display...
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