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Patent # Description
US-1,009,6608 Semiconductor device including memory cell array and power supply region
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second...
US-1,009,6607 Three-dimensional stacked junctionless channels for dense SRAM
A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked...
US-1,009,6606 Methods of forming a gate structure-to-source/drain conductive contact on vertical transistor devices and the...
In one example, the method includes removing a portion of at least a layer of a bottom spacer material positioned above a first bottom source/drain (S/D) region...
US-1,009,6605 Semiconductor devices including a dummy gate structure on a fin
Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The...
US-1,009,6604 Selective SAC capping on fin field effect transistor structures and related methods
FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality...
US-1,009,6603 Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns,...
US-1,009,6602 MTP memory for SOI process
Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin ...
US-1,009,6601 Stacked three-dimensional arrays of two terminal nanotube switching devices
Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and...
US-1,009,6600 Semiconductor device with metal gate
A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, a...
US-1,009,6599 Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process
Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for...
US-1,009,6598 Methods for fabricating fin field effect transistors
Methods for fabricating Fin field effect transistors (FinFETs) are disclosed. First and second semiconductor fins and an insulator therebetween are formed....
US-1,009,6597 Re-grown gate structure and fabrication method thereof
A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate...
US-1,009,6596 Semiconductor device structure having a plurality of gate structures
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a...
US-1,009,6595 Antenna diode circuit for manufacturing of semiconductor devices
At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a...
US-1,009,6594 Display panel and display device having the same
A display panel includes: an electrostatic discharge (ESD) protection circuit area in a peripheral area surrounding a display area including pixels, the ESD...
US-1,009,6593 Semiconductor integrated circuit device having an ESD protection circuit
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring...
US-1,009,6592 OLED lighting device with short tolerant structure
An OLED panel having a plurality of OLED circuit elements is provided. Each OLED circuit element may include a fuse or other component that can be ablated or...
US-1,009,6591 Semiconductor device having an electrostatic protection element
In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric...
US-1,009,6590 Sensor device including diode elements connected in series in opposite directions to each other
In conventional sensor devices, it has been difficult to achieve both EMC resistance and ESD resistance, which are required at the output terminals of an...
US-1,009,6589 Fin ESD protection diode and fabrication method thereof
A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by...
US-1,009,6588 TVS structures for high surge and low capacitance
A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device...
US-1,009,6587 Fin-based diode structures with a realigned feature layout
Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to...
US-1,009,6586 LED display modules and methods for making the same
An LED display module is disclosed. The LED display module includes: an active matrix substrate including a plurality of control units; a plurality of pairs of...
US-1,009,6585 Method of manufacturing light emitting element and light emitting device including forming resin film including...
A method of manufacturing a light emitting element includes forming a resin film including a phosphor containing layer on a transparent board side surface of a...
US-1,009,6584 Method for producing a power semiconductor module
In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element....
US-1,009,6583 Method for fabricating a semiconductor integrated chip
The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection...
US-1,009,6582 Enhanced power distribution to application specific integrated circuits (ASICS)
Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a...
US-1,009,6581 Light emitting module
A light emitting module according to an embodiment includes a first insulation film with a light transmissivity, a second insulation film disposed so as to face...
US-1,009,6580 Illumination assembly, method of manufacturing the Illumination assembly, and backlight module including the...
An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed...
US-1,009,6579 Thermal pads between stacked semiconductor dies and associated systems and methods
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the...
US-1,009,6578 Semiconductor package device and method of manufacturing the same
A semiconductor package device includes a substrate, an electronic component disposed on the substrate, and a package body. The electronic component has a first...
US-1,009,6577 Semiconductor memory package including stacked layers and memory device and semiconductor memory system having...
A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer;...
US-1,009,6576 Semiconductor device assemblies with annular interposers
A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of...
US-1,009,6574 Semiconductor device including protective film over a substrate
A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective...
US-1,009,6573 Face-to-face semiconductor assembly having semiconductor device in dielectric recess
A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of...
US-1,009,6572 Power semiconductor module and electric power steering apparatus using the same
A power semiconductor module that comprises plural arrangements of power semiconductor elements comprising a power semiconductor bare chip which one electrode...
US-1,009,6571 Chip-on-wafer package and method of forming same
A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the...
US-1,009,6570 Manufacturing method for power semiconductor device, and power semiconductor device
An object of the invention is to provide: a manufacturing method for a highly reliable power semiconductor device which prevents breakage of an conductor...
US-1,009,6569 Semiconductor device and method for manufacturing the same
The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a...
US-1,009,6568 Die bonding tool and system
Disclosed is a die bonding tool comprising: a rigid body; and a collet having a die-holding portion; wherein the collet is mechanically coupled to the rigid...
US-1,009,6567 Package substrate and package
A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided....
US-1,009,6566 Semiconductor device
A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and...
US-1,009,6565 Method for fabricating glass substrate package
A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the...
US-1,009,6564 Manufacturing method of semiconductor package
A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top...
US-1,009,6563 Semiconductor package and method of forming the same
A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the...
US-1,009,6562 Power module package
A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit...
US-1,009,6561 Integrated circuit die having a split solder pad
An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising...
US-1,009,6560 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip...
US-1,009,6559 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip...
US-1,009,6558 Multi-band antenna package structure, manufacturing method thereof and communication device
A multi-band antenna package structure includes a first redistribution layer; an integrated circuit layer, formed on the first redistribution layer, comprising...
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