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Patent # Description
US-1,009,6557 Tiled-stress-alleviating pad structure
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad...
US-1,009,6556 Semiconductor device
A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair...
US-1,009,6555 Shielded QFN package and method of making
Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN...
US-1,009,6554 Semiconductor device having an epitaxial layer and manufacturing method thereof
A mark is formed over the surface of a silicon substrate. The mark includes a silicon oxide film, in which a plurality of rectangular groove patterns are...
US-1,009,6553 Metal pad for laser marking
A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the...
US-1,009,6552 Fan-out semiconductor package
A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution...
US-1,009,6551 Electronic component of integrated circuitry and a method of forming a conductive via to a region of...
An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface....
US-1,009,6550 Nitride structure having gold-free contact and methods for forming such structures
A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the...
US-1,009,6549 Semiconductor devices having interconnection structure
Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact...
US-1,009,6548 Method of manufacturing Cu wiring
In a Cu wiring manufacturing method, a MnO.sub.x film which becomes a self-formed barrier film by reaction with an interlayer insulating film of a substrate is...
US-1,009,6547 Metallic interconnects products
One embodiment is a semiconductor device including: at least one patterned dielectric layer having at least one opening therein, said at least one opening...
US-1,009,6546 Semiconductor device
A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the...
US-1,009,6545 Semiconductor apparatus, system, and method of manufacturing semiconductor apparatus
There is provided an image capturing apparatus including a pixel circuit that generates a pixel signal based on an electric charge generated by photoelectric...
US-1,009,6544 Semiconductor interconnect structure
The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a...
US-1,009,6543 Semiconductor capacitor structure for high voltage sustain
The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer...
US-1,009,6542 Substrate, semiconductor package structure and manufacturing process
A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is...
US-1,009,6541 Method for fabricating electronic package
A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality...
US-1,009,6540 Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for...
A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed...
US-1,009,6539 Lead frame and electronic component device
A lead frame includes: a resin portion including an upper surface and a lower surface opposite to the upper surface; and a first terminal formed to penetrate...
US-1,009,6538 Cooling of wide bandgap semiconductor devices
A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the...
US-1,009,6537 Thermal management systems, methods for making, and methods for using
Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal...
US-1,009,6536 Graphene heat dissipating structure
Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein...
US-1,009,6535 Packaged semiconductor die and CTE-engineering die pair
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For...
US-1,009,6534 Thermal performance of logic chip in a package-on-package structure
Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the...
US-1,009,6533 Multiple barrier layer encapsulation stack
A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying...
US-1,009,6531 Semiconductor device with sensor potential in the active region
A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first...
US-1,009,6530 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill...
US-1,009,6529 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill...
US-1,009,6528 Critical dimension control by use of a photo agent
A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the...
US-1,009,6527 Hybrid corrective processing system and method
A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data...
US-1,009,6526 Die bonder and bonding method
A bonding method of a die bonder with a single conveyance lane and a single bonding head, or a plurality of conveyance lanes and a plurality of bonding heads...
US-1,009,6525 Method for fabricating self-aligned contact in a semiconductor device
A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall...
US-1,009,6524 Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors
Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate,...
US-1,009,6523 Spacer structure and manufacturing method thereof
A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are...
US-1,009,6522 Dummy MOL removal for performance enhancement
The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an...
US-1,009,6521 SRAM design to facilitate single fin cut in double sidewall image transfer process
A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by...
US-1,009,6520 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming...
US-1,009,6519 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a...
US-1,009,6518 Semiconductor structures and fabrication methods thereof
Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of...
US-1,009,6517 Wafer processing method
Disclosed herein is a wafer processing method for dividing a wafer into individual device chips along division lines. The wafer processing method includes a...
US-1,009,6516 Method of forming a barrier layer for through via applications
Embodiments of the disclosure generally relate to a method of improving quality of a barrier layer suitable for forming high aspect ratio through substrate...
US-1,009,6515 Interconnect structure for stacked device
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes...
US-1,009,6514 Seamless trench fill using deposition/etch techniques
Methods for filing a feature on a substrate surface comprising depositing a conformal nitride film on the substrate surface and at least one feature on the...
US-1,009,6513 Direct plasma densification process and semiconductor devices
An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a...
US-1,009,6512 Gapfill film modification for advanced CMP and recess flow
Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is...
US-1,009,6511 Carrier and a method for processing a carrier
According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench...
US-1,009,6510 Semiconductor device and method of manufacturing same
To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a...
US-1,009,6509 Substrate carrier system with protective covering
Embodiments disclosed herein generally relate to a substrate carrier system suitable for clamping a substrate and optionally a mask, the substrate carrier...
US-1,009,6508 Assembly for handling a semiconductor die and method of handling a semiconductor die
In various embodiments, an assembly for handling a semiconductor die is provided. The assembly may include a carrier with a surface. The assembly may also...
US-1,009,6507 Thin substrate electrostatic chuck system and method
In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate...
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