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Patent # Description
US-1,009,5648 Cantilevered network interface card assembly having port connector accessible from region outside of computing...
An apparatus includes a circuit card substrate that is associated with a network interface card. The circuit card substrate includes a connector edge to be...
US-1,009,5647 Accelerator architecture on a programmable platform
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors...
US-1,009,5646 Device and method for allowing integration of incompatible devices into a vehicle bus network
A device and method for communication among vehicle components operating on different electronic vehicle bus communication protocols is disclosed. The current...
US-1,009,5645 Presenting multiple endpoints from an enhanced PCI express endpoint device
A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor...
US-1,009,5644 Data transfer device and wireless communication circuit
Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device...
US-1,009,5643 Direct memory access control device for at least one computing unit having a working memory
A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system...
US-1,009,5642 Data accessing system and method for the same
The invention provides a data accessing system and a method for the same. The data accessing system comprises a data access unit and a data storage unit. When...
US-1,009,5641 Processor with frames/bins structure in local high speed memory
A computing device includes a main memory; a local high speed memory; one or more functional units, one or more interconnects between the main memory and the...
US-1,009,5640 Multi mode address spaces for PC to device transfer optimization
A computer-implemented method for transferring data over a bus from a host to a device is presented. The method includes determining a size of the data to be...
US-1,009,5639 Multi-processor startup system
A switch includes a PCI bus. A line card processor is coupled to a line card memory system and includes a line card processor port connected to the PCI bus. A...
US-1,009,5638 Memory system capable of wireless communication and method of controlling memory system
According to one embodiment, a memory controller allows access to a first non-volatile memory from a host device when a wireless communication unit is...
US-1,009,5637 Speculative retirement of post-lock instructions
Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire...
US-1,009,5636 Secure computing
Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The...
US-1,009,5635 Securing information relating to data compression and encryption in a storage device
Apparatus and method for data security in a data storage environment. In some embodiments, input data from a host is received into a buffer memory. Data...
US-1,009,5634 In-vehicle network (IVN) device and method for operating an IVN device
Embodiments of a device and method are disclosed. In an embodiment, an IVN transceiver is disclosed. The IVN transceiver includes an IVN bus interface, a...
US-1,009,5633 Cache longevity detection and refresh
A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving...
US-1,009,5632 Memory affinity management
Disclosed aspects relate to memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA). An...
US-1,009,5631 System address map for hashing within a chip and between chips
A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected...
US-1,009,5630 Sequential access to page metadata stored in a multi-level page table
Systems and methods enable initializing and accessing page metadata stored in the last level of a multi-level page table, wherein an effort is made to reduce...
US-1,009,5629 Local and remote dual address decoding using caching agent and switch
Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more...
US-1,009,5628 Considering a density of tracks to destage in groups of tracks to select groups of tracks to destage
Provided are a computer program product, system, and method for considering a density of tracks to destage in groups of tracks to select groups of tracks to...
US-1,009,5627 Method and system for efficient communication and command system for deferred operation
A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command...
US-1,009,5626 Multibit NAND media using pseudo-SLC caching technique
A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes...
US-1,009,5625 Storage system and method for controlling cache
When one of a plurality of storage apparatuses receives an input/output (IO) request in which the address of a logical volume is designated, a cache destination...
US-1,009,5624 Intelligent cache pre-fetch
An intelligent cache pre-fetch system includes a pre-fetch throttling scheme to monitor a cache hit rate context. Pre-fetch reads of additional data are only...
US-1,009,5623 Hardware apparatuses and methods to control access to a multiple bank data cache
Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to...
US-1,009,5622 System, method, and apparatuses for remote monitoring
Embodiments of systems, method, and apparatuses for remote monitoring are described. In some embodiments, an apparatus includes at least one monitoring circuit...
US-1,009,5621 Coordination of cache and memory reservation
A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least...
US-1,009,5620 Computer system including synchronous input/output and hardware assisted purge of address translation cache...
A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address...
US-1,009,5619 Universal cache management system
Techniques for universal cache management are described. In an example embodiment, a plurality of caches are allocated, in volatile memory of a computing...
US-1,009,5618 Memory card with volatile and non volatile memory space having multiple usage model configurations
An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory...
US-1,009,5617 Memory device with flexible data transfer rate interface and method thereof
A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory...
US-1,009,5616 Garbage collection for virtual environments
Embodiments disclosed herein provide systems and methods for performing garbage collection in virtual environments. In a particular embodiment, a method...
US-1,009,5615 Garbage collection based on total resource usage and managed object metrics
A method includes selectively controlling, at a computing device having a memory, initiation of a full garbage collection operation based on a total resource...
US-1,009,5614 Memory controller and accessing system utilizing the same
A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is...
US-1,009,5613 Storage device and data processing method thereof
A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data...
US-1,009,5612 Storage ballooning in a mobile computing device
One embodiment of the present invention provides a system for managing storage space in a mobile device. During operation, the system detects a decrease in...
US-1,009,5611 Methodology for unit test and regression framework
Disclosures herein describe a record and replay regression and unit test automation framework for simulating any hardware on a virtual machine to achieve...
US-1,009,5610 Testing applications with a defined input format
A system and method are provided for testing the performance of applications. By way of example only, the method may include training a neural network with...
US-1,009,5609 Intermediary for testing content and applications
A test device may include an application that accesses online content. In some examples, a test intermediary and/or a test user interface (UI) are downloaded to...
US-1,009,5608 Application test automation transmitting data via phone/voice calls
An application for testing is determined. A test script associated with the application for testing is determined. The application is tested using the test...
US-1,009,5607 Information processing device, computer program product, and testing system with acquiring total execution history
A condition determination device includes an acquiring unit, a specifying unit, a classifying unit, and a condition determining unit. The acquiring unit...
US-1,009,5606 Guest-independent testing of guest firmware in virtualized systems
A system and methods are disclosed for testing guest firmware in virtualized computer systems. In accordance with one embodiment, a hypervisor executed by a...
US-1,009,5605 Debugger write interceptor
Methods, systems, and computer program products are included for executing one or more instructions of a program in a debugging session; receiving a command at...
US-1,009,5604 Creating trace data from recent software output and activity
Creating additional trace entries by dynamically processing recently captured output data, working data, and input data to diagnose a software error....
US-1,009,5603 Pre-fetching disassembly code for remote software debugging
A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the...
US-1,009,5602 Automated code analyzer
A system for analyzing source code may include a computer including a memory and a processor. A discoverer may be stored on the memory and may be configured to...
US-1,009,5601 Triple software redundancy fault tolerant framework architecture
A computer implemented method of detecting a fault in a system comprises the steps of executing at least three virtual machines, each virtual machine executing...
US-1,009,5600 Real-time globalization verification on development operations
Technical solutions are described for verifying translatability compliance of a new code for a computer program product includes receiving a notification about...
US-1,009,5599 Optimization for application runtime monitoring
This disclosure provides a computer-implemented method for monitoring an application at runtime. The method comprises building up a calling relationship graph...
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