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Patent # Description
US-1,010,3147 Vertical transport transistors with equal gate stack thicknesses
Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and...
US-1,010,3146 FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same
A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET...
US-1,010,3145 Two dimension material fin sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls....
US-1,010,3144 Two dimension material fin sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls....
US-1,010,3143 Fin transistor, method for fabricating the same and electronic device including the same
An electronic device is provided. The electronic device comprises a fin transistor formed over a substrate which is structured to include a device isolation...
US-1,010,3142 Integrated circuit (IC) devices including stress inducing layers
Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and...
US-1,010,3141 Fin deformation modulation
A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor...
US-1,010,3140 Switch circuit with controllable phase node ringing
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a...
US-1,010,3139 Method and design of low sheet resistance MEOL resistors
An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active...
US-1,010,3138 Dual-sided silicon integrated passive devices
In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface...
US-1,010,3137 Field effect transistor (FET) structure with integrated gate connected diodes
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect...
US-1,010,3136 Electrostatic discharge protection semiconductor device
An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate...
US-1,010,3135 Backside ground plane for integrated circuit
An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate...
US-1,010,3134 Methods of manufacturing multi-die semiconductor device packages and related assemblies
Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first...
US-1,010,3133 Packaging of high performance system topology for NAND memory systems
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the...
US-1,010,3132 Semiconductor device and method of manufactures
A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through...
US-1,010,3131 LED Module and method for fabricating the same
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding...
US-1,010,3130 LED module
An LED module includes a substrate, one or more LED chips supported by a main surface of the substrate, and wirings. The substrate has one or more through holes...
US-1,010,3129 Data storage device having multi-stack chip package and operating method thereof
A data storage device includes a controller and a multi-stack chip package. A method is used to operate the data storage device. The multi-stack chip package...
US-1,010,3128 Semiconductor package incorporating redistribution layer interposer
A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack...
US-1,010,3126 Laminated semiconductor device and manufacturing method of laminated semiconductor device
A laminated semiconductor device includes: three or more semiconductor chips that are laminated; resins that are disposed among the semiconductor chips, the...
US-1,010,3125 Chip package structure and method for forming the same
A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the...
US-1,010,3124 Semiconductor device
A semiconductor device includes a first semiconductor chip including plural circuit blocks provided on a semiconductor substrate, and plural through-silicon...
US-1,010,3123 Semiconductor devices and processing methods
Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed...
US-1,010,3122 Hybrid bonding systems and methods for semiconductor wafers
Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a...
US-1,010,3121 Tall and fine pitch interconnects
Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board...
US-1,010,3120 Semiconductor device including a buffer layer structure for reducing stress
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different...
US-1,010,3119 Methods of forming integrated circuit structure for joining wafers and resulting structure
The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar...
US-1,010,3118 Fabrication of solder balls with injection molded solder
Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal...
US-1,010,3117 Method of manufacturing fan-out type wafer level package
Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a...
US-1,010,3116 Open-passivation ball grid array pads
A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive...
US-1,010,3115 Circuit substrate and semicondutor package structure
A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit...
US-1,010,3114 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad,...
US-1,010,3113 Method of manufacturing printed circuit board
A step of forming bump pads on the surface of the substrate corresponding to the cavity region, and covering the whole surface with a second insulating layer,...
US-1,010,3112 Circuit board with measure against high frequency noise
A circuit board with a measure against high frequency noise includes: an interconnect substrate having an interconnect pattern to which an IC which is a source...
US-1,010,3111 Semiconductor chip having tampering feature
Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device...
US-1,010,3110 Semiconductor package structure and fabrication method thereof
A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate...
US-1,010,3109 Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device
Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the...
US-1,010,3108 Nanostructured chip and method of producing the same
A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the...
US-1,010,3107 Semiconductor device and method for manufacturing the same
A semiconductor device includes at least one base element, at least one passivation layer, at least one circuit layer and at least one light absorbing layer....
US-1,010,3106 Wafer level fan-out with electromagnetic shielding
The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output...
US-1,010,3105 High density organic bridge device and method
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
US-1,010,3104 Package carrier and manufacturing method of package carrier
A package carrier including a flexible substrate, a first build-up structure and a second build-up structure is provided. The flexible substrate has a first...
US-1,010,3103 Bridge interconnection with layered interconnect structures
Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in...
US-1,010,3102 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a...
US-1,010,3101 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first...
US-1,010,3100 Semiconductor device
The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit...
US-1,010,3099 Semiconductor devices and methods of forming same
Embodiments of the present disclosure include a semiconductor device and methods of forming the same. A representative embodiment includes a method of forming a...
US-1,010,3098 Semiconductor devices including a through via structure and methods of forming the same
Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor...
US-1,010,3097 CD control
A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD...
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