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Patent # Description
US-1,010,3096 Semiconductor device
A semiconductor device (10) of the present invention includes at least one circuit unit (41, 42, 43) which includes: a device main body (20); and a power supply...
US-1,010,3095 Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a...
US-1,010,3094 Method and structures for heat dissipating interposers
An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive...
US-1,010,3093 Via structure for signal equalization
An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first...
US-1,010,3092 Multilayer substrate, component mounted board, and method for producing component mounted board
A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal...
US-1,010,3091 Semiconductor device
A semiconductor device may include: a first and a second semiconductor elements each including electrodes on both surfaces thereof; a first and a second metal...
US-1,010,3090 Semiconductor device
The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode...
US-1,010,3089 Heat transfer device with fins defining air flow channels
An exemplary cooling system includes a heat transfer device having a base and a plurality of curved fins defining a curved air flow channel. Air flow is...
US-1,010,3088 Integrated antenna for direct chip attach connectivity module package structures
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a...
US-1,010,3087 Heat dissipation assembly and electronic device
The present invention provides a heat dissipation assembly and an electronic device, where the heat dissipation assembly includes: a shielding element, where a...
US-1,010,3086 Fixing frame for heat sink
A fixing frame for a heat sink includes boards, at least one foldable plate, and connection members. The boards surround a hollow area, and the hollow area...
US-1,010,3085 Clamping assembly having a pressure element
A clamping assembly includes a configuration of mechanically clamped components disposed one on top of the other to form a stack. A clamping device generates a...
US-1,010,3084 System and method for clamping press pack high power semiconductor
Systems and methods for setting, assembling, and/or monitoring deflection (and thus load) in a load beam of a clamping system for a press pack high power...
US-1,010,3083 Integrated circuits with Peltier cooling provided by back-end wiring
A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more...
US-1,010,3082 Semiconductor device and manufacturing method therefor
The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The...
US-1,010,3081 Heat sink
A heat sink (100) for an electronic device comprising a first plate (102), a second plate (104) and a pipe (106). One side of the first plate (102) is in...
US-1,010,3080 Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
US-1,010,3079 Electronic device provided with an integral conductive wire and method of manufacture
An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to...
US-1,010,3078 Formation of getter layer for memory device
A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a...
US-1,010,3077 Sealing cap for electronic component
An electronic component cap for producing a package having a sealed region by being bonded to a base, having a brazing material-fused surface to which a brazing...
US-1,010,3076 Semiconductor package including a semiconductor die having redistributed pads
A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and...
US-1,010,3075 Semiconductor device and manufacturing method thereof
When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a...
US-1,010,3074 Method to improve analog fault coverage using test diodes
Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a...
US-1,010,3073 Inductive monitoring of conductive trench depth
In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of...
US-1,010,3072 Damaging components with defective electrical couplings
A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple,...
US-1,010,3071 Pattern inspection methods and methods of fabricating reticles using the same via directing charged particle...
A reticle may be fabricated and inspected. The reticle, which may include thin patterns, may be selectively incorporated into a fabricated semiconductor device...
US-1,010,3070 Dynamic integrated circuit fabrication methods
Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a...
US-1,010,3069 Pressure-activated electrical interconnection by micro-transfer printing
A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one...
US-1,010,3068 Detecting a void between a via and a wiring line
A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and...
US-1,010,3067 Semiconductor device comprising trench isolation
A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a...
US-1,010,3066 Method of utilizing trench silicide in a gate cross-couple construct
A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and...
US-1,010,3065 Gate metal patterning for tight pitch applications
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs,...
US-1,010,3064 Transistor structure including epitaxial channel layers and raised source/drain regions
The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain...
US-1,010,3063 Forming a hybrid channel nanosheet semiconductor structure
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner...
US-1,010,3062 Method for fabricating semiconductor device having gate structure
A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top...
US-1,010,3061 Processing method of single-crystal substrate
Disclosed herein is a processing method of a single-crystal substrate having a film formed on a front side or a back side thereof to divide the single-crystal...
US-1,010,3060 Test structures for dielectric reliability evaluations
Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of...
US-1,010,3059 Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity...
US-1,010,3058 Tungsten feature fill
Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as...
US-1,010,3057 Use of an inhibitor molecule in chemical vapor deposition to afford deposition of copper on a metal substrate...
Provided herein are methods for selectively forming layers of metal films on one portion of a substrate while leaving adjacent portions of the substrate...
US-1,010,3056 Methods for wet metal seed deposition for bottom up gapfill of features
A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of...
US-1,010,3055 Expansion sheet, expansion sheet manufacturing method, and expansion sheet expanding method
An expansion sheet is adapted to be held and expanded by an expanding apparatus when a platelike workpiece is attached to the expansion sheet. The expansion...
US-1,010,3054 Coupled vias for channel cross-talk reduction
Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall...
US-1,010,3053 Methods of forming integrated circuitry
Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the...
US-1,010,3052 Method for manufacturing a structure by direct bonding
The method includes the steps of: a) providing first and second layers, each including a bonding surface, at least one of said layers including recesses and the...
US-1,010,3051 Semiconductor structure having an isolation layer for reducing parasitic effect
A semiconductor structure includes a first well, a semiconductor element, a second well and a first isolation layer. The semiconductor element is formed on or...
US-1,010,3050 System reference with compensation of electrical and mechanical stress and life-time drift effects
Stress compensated systems and methods of compensating for electrical and mechanical stress are discussed. One example system can include a first circuit and a...
US-1,010,3049 Method and apparatus for preventing the deformation of a substrate supported at its edge area
The method and the apparatus prevents the deformation of a substrate, e.g. a wafer, supported with its edge area or periphery at a support or chuck, and also...
US-1,010,3048 Dual-layer bonding material process for temporary bonding of microelectronic substrates to carrier substrates
A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between...
US-1,010,3047 Flow path member, heat exchanger including the flow path member, and semiconductor manufacturing apparatus...
A flow path member includes a flow path which has an inlet and an outlet in a base made of ceramics, and a low resistance portion whose surface resistance is...
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