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Patent # Description
US-1,010,2190 Memory conserving versioning of an electronic document
Memory conserving versioning of an electronic document is provided. Client versioning factors are analyzed by a client versioning engine and server versioning...
US-1,010,2189 Construction of a phonetic representation of a generated string of characters
Provided are methods, devices, and computer-readable media for generating a string of characters based on a set of rules; parsing the string of characters into...
US-1,010,2188 ODatadoc generation from OData metadata document
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a common schema definition language...
US-1,010,2187 Extensible framework for ereader tools, including named entity information
Information about named entities referenced in an electronic book (ebook) is provided to a client device. An ebook identifier identifying the ebook is received...
US-1,010,2186 System for and method of providing a user interface for a computer-based software application
A system for providing a graphical interface to a user includes a server platform and an operating system and application software running thereon. The system...
US-1,010,2185 Digital document including reference page numbers and fractional page numbers
A device including a processor and a memory communicatively coupled to the processor is provided. The memory stores instructions causing the processor, after...
US-1,010,2184 Allowing operating system access to non-standard fonts in a network document
When a browsing computer navigates to a network document, such as a web page, the corresponding server also downloads computer readable formatting information...
US-1,010,2183 System for transferring annotations between documents displayed side by side
A system and method to view, edit, share, and organize files using software in the form of a computing application for a computing device, allowing a user to...
US-1,010,2182 Indicators of text continuity
Methods, systems, and apparatus, including computer programs encoded on computer storage media for graphically indicating text continuity. One method includes...
US-1,010,2181 Efficient Catmull-Rom interpolation
Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without...
US-1,010,2180 Majority circuit
An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for...
US-1,010,2179 Multiple core computer processor with globally-accessible local memories
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of...
US-1,010,2178 Remotely powered, multisite sensing system with a shared, two-wire bus for power and communication
A multisite sensing system including two or more analyte sensors, an interface device, and a shared bus. The interface device may be configured to receive a...
US-1,010,2177 Serial communication system, communication control unit, and electronic device for finding and assigning unused...
To provide a serial communication system that can flexibly or easily change a system configuration. For example, when coupled to first and second serial buses,...
US-1,010,2176 Methods and apparatus for rapid switching of hardware configurations with a speed limited bus
Methods and apparatus for enabling rapid transactions over a speed limited bus are disclosed. In one exemplary embodiment of the present disclosure, a host...
US-1,010,2175 Methods and apparatus for multi-drop digital bus
Apparatus and methods for digital bus operation. In one embodiment, the digital bus is a bidirectional, time-division multiplexing (TDM) audio bus operation,...
US-1,010,2174 Smart harness
A smart harness may comprise a connector configured to selectively plug into and be removable from an Electronic Control Unit ("ECU") of a vehicle, a first...
US-1,010,2173 Pending load based frequency scaling
Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a...
US-1,010,2172 Method and apparatus for performing a single pass compilation for systems with dynamically reconfigurable logic...
A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base...
US-1,010,2171 Method of handling transactions, corresponding system and computer program product
A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or...
US-1,010,2170 System and method for providing input/output functionality by an I/O complex switch
An input/output (I/O) device includes a management controller interface, a plurality of network switching interfaces, a storage interface, a component...
US-1,010,2169 System and method for port migration in a PCIE switch
The present disclosure provides a method and system for dynamically migrating a port in a PCIe switch. The PCIe switch comprises emulated P2P bridges stored in...
US-1,010,2168 Scalable low-latency mesh interconnect for switch chips
A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a...
US-1,010,2167 Data processing circuit and data processing method
This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control...
US-1,010,2166 Multiprocessor system
The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor...
US-1,010,2165 Arbitration in an SRIOV environment
In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output...
US-1,010,2164 Multiple-queue integer coalescing mapping algorithm with shared based time
A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at...
US-1,010,2163 Bus participant device and method for operating a bus subscriber device
The invention relates to a bus participant device (30) for receiving and transmitting data telegrams (18) via a serial data bus (12) according to a master/slave...
US-1,010,2162 Method and apparatus for processing adaptive interrupt, host employing the same, I/O device and system
Processing an adaptive interrupt includes selectively setting an input/output (I/O) device in a computing system to an adaptive masking mode when at least one...
US-1,010,2161 Microcomputer
A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes...
US-1,010,2160 Speculative interrupt signalling
A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the...
US-1,010,2159 Method of achieving low write latency in a data storage system
A data storage system includes a host having a write buffer, a memory region, a submission queue and a driver therein. The driver is configured to: (i) transfer...
US-1,010,2158 Methods and apparatus for processing multiple streams of data
Methods and apparatus relating to the transfer of data for processing and/or the transfer of the resulting processed data are described. Some features relate to...
US-1,010,2157 Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and...
A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in...
US-1,010,2156 Display apparatus, display control method, and computer readable recording medium
A display apparatus including a display that displays messages includes a message retrieval unit that retrieves messages by accessing a message management...
US-1,010,2155 Method and device of information protection for micro control unit chip
The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data...
US-1,010,2154 Protected memory area
In some examples, in response to a computing device powering on, a protected memory area inaccessible to an operating system is created, where the protected...
US-1,010,2153 System and method for intercept of UEFI block I/O protocol services for BIOS based hard drive encryption support
An information handling system and method performs Unified Extensible Firmware Interface (UEFI) interception and pre-processing of data associated with block...
US-1,010,2152 Protecting a memory from unauthorized access
A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in...
US-1,010,2151 Protecting a memory from unauthorized access
A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in...
US-1,010,2150 Adaptive smart data cache eviction
An adaptive smart data cache eviction method takes file-based quotas into account during eviction of WEUs as opposed to a default eviction policy that treats...
US-1,010,2149 Replacement policies for a hybrid hierarchical cache
A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time,...
US-1,010,2148 Page-based compressed storage management
A memory is made up of multiple pages, and different pages can have different priority levels. A set of memory pages having at least similar priority levels are...
US-1,010,2147 Phased based distributed LRU for shared cache systems
In a system in which a plurality of computing elements share a cache, each computing element owns a stripe of the cache. Each stripe contains cache objects that...
US-1,010,2146 Memory system and operating method for improving rebuild efficiency
Methods may include after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to...
US-1,010,2145 Out of order LBA processing
Systems and methods are disclosed to perform out of order LBA processing at a data storage device. A data storage device may be configured to receive a read...
US-1,010,2144 Systems, methods and interfaces for data virtualization
A data services module performs log storage operations in response to requests by storing data on one or more storage devices, and appending information...
US-1,010,2143 Eviction control for an address translation cache
A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a...
US-1,010,2142 Virtual address based memory reordering
A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an...
US-1,010,2141 System and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
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