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Patent # Description
US-1,010,2140 Methods and apparatuses for addressing memory caches
A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third...
US-1,010,2139 Memory management for address translation including detecting and handling a translation error condition
A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises:...
US-1,010,2138 Division of data storage in single-storage device architecture
Systems and methods are disclosed for sub-dividing data in non-volatile data storage modules. A data storage device includes a non-volatile memory comprising a...
US-1,010,2136 Electronic device and method for fabricating the same
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate including a first region and a second...
US-1,010,2135 Dynamically-adjusted host memory buffer
Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the...
US-1,010,2134 Instruction and logic for run-time evaluation of multiple prefetchers
A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The...
US-1,010,2133 Reducing latency by caching derived data at an edge server
To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata...
US-1,010,2132 Data transfer in a multiprocessor using a shared cache memory
Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a...
US-1,010,2131 Proactive power management for data storage devices to reduce access latency
Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store...
US-1,010,2130 Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of...
A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system...
US-1,010,2129 Minimizing snoop traffic locally and across cores on a chip multi-core fabric
A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality...
US-1,010,2128 Locks to enable updating data and a data replacement order in cache areas
Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at...
US-1,010,2127 Locks to enable updating data and a data replacement order in cache areas
Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at...
US-1,010,2126 Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one...
US-1,010,2125 PCI device, interface system including the same, and computing system including the same
A peripheral component interconnect (PCI) device includes a first memory which includes a plurality of page buffers, a base address register which includes a...
US-1,010,2124 High bandwidth full-block write commands
A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high...
US-1,010,2123 Hybrid hardware and software implementation of transactional memory access
Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a...
US-1,010,2122 Personal computing device for editing mainframe data
A personal computer executes a productivity application that communicates with a mainframe computer via a communications network. The productivity application...
US-1,010,2121 Memory management method, memory control circuit unit and memory storage device
A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: configuring a plurality of first type...
US-1,010,2120 Hybrid garbage collection for multi-version concurrency control in database systems
Technologies for performing garbage collection in database systems, such as multi-version concurrency control (MVCC) database systems, are described. For...
US-1,010,2119 Garbage collection based on queued and/or selected write commands
A non-volatile memory system may include a write task queue that queues write commands and a garbage collection module that analyzes information about pending...
US-1,010,2118 Memory system and non-transitory computer readable recording medium
According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The...
US-1,010,2117 Systems and methods for cache and storage device coordination
A cache module leverages storage metadata to cache data of a backing store on a non-volatile storage device. The cache module maintains access metadata...
US-1,010,2116 Multi-level page data structure
Methods, systems, and computer program products for receiving a memory allocation request; comparing a memory size corresponding to the memory allocation...
US-1,010,2115 Incremental program construction from embedded program code for external testing
An application can include program code in multiple programming languages. Typically, a primary or host application program code will include secondary program...
US-1,010,2114 Code testing and approval for deployment to production environment
A system for testing candidate code to determine if the candidate code is approved for deployment to a production environment. The system may include a code...
US-1,010,2113 Software test automation systems and methods
Described are a system and method for performing an automated quality assessment on a software program under test. A test automation system executes a test on a...
US-1,010,2112 Method and system for generating test strategy for a software application
The present disclosure relates to a method for generating test strategy for a software application. The test strategy generation system receives a plurality of...
US-1,010,2111 Prioritizing resiliency tests of microservices
Techniques are provided for automated resiliency testing. In one example, a computer-implemented method comprises analyzing, by a system operatively coupled to...
US-1,010,2110 Simulation process for interface behavior
An interface behavior simulator communications processor is provided for operating on a non-transitory computer platform for analyzing and sending a message...
US-1,010,2109 Exception resolution in a software development session
Mechanisms for exception resolution in a software development session are provided. An exception is detected during a software development session. Information...
US-1,010,2108 Injected instrumentation application monitoring and management
Techniques to instrument computer applications to receive run-time telemetry, and to perform analysis on collected telemetry are described. Telemetry...
US-1,010,2107 Source code migration tool
A source code migration tool comprising a memory, a receiver, a resolved source code file generation engine, and a verification engine. The memory is configured...
US-1,010,2106 Promotion determination based on aggregated code coverage metrics
Techniques are described for aggregating code coverage data generated from various types of testing of software modules, and automatically determining whether...
US-1,010,2105 Determining code complexity scores
In one example of the disclosure, code lines for a software program are received, the code lines including a unit of code lines. Code entities within the unit...
US-1,010,2104 Thread dump viewer
A thread dump viewer presents information for a plurality of threads. The information about the threads can be presented in a table view. The thread dump viewer...
US-1,010,2103 System resource component utilization
A computer implemented method including receiving a set of utilization metrics for a system comprising at least an average number of concurrent requests to the...
US-1,010,2102 Characterizing device performance based on user-perceivable latency
A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric...
US-1,010,2101 Methods, systems, and computer readable mediums for determining a system performance indicator that represents...
Methods, systems, and computer readable mediums for determining a system performance indicator representative of the overall operation of a network system are...
US-1,010,2100 Optimizing automated interactions with computer software applications
Performing an automated interaction with a computer software application by identifying, among a plurality of regions of an interface of a computer software...
US-1,010,2099 Performance information generating method, information processing apparatus and computer-readable storage...
A performance information generating method, the method includes: reading, by a computer, context information generated by a context information collection...
US-1,010,2098 Method and system for recommending application parameter setting and system specification setting in...
A method and a system for recommending an application parameter setting and a system specification setting in a distributed computation are provided. The method...
US-1,010,2097 Transaction server performance monitoring using component performance data
Embodiments of the present invention provide a method, system and computer program product for predicting transaction server performance failure in a...
US-1,010,2096 Method and apparatus for GPS based Z-axis difference parameter computation
Data is collected during the operation of a vehicle and used to produce a ranking of a driver's efficiency performance, and that ranking is shared on a hosted...
US-1,010,2095 Peripheral management system, management device, and management method
There is provided a peripheral management system including a client terminal which a peripheral can be connected to and a management device which manages the...
US-1,010,2094 Simulating legacy bus behavior for backwards compatibility
To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance...
US-1,010,2093 Methods and systems for determining an equipment operation based on historical operation data
This disclosure relates generally to data processing, and more particularly, to methods and systems for determining an equipment operation based on historical...
US-1,010,2092 Testing front end module, testing methods and modular testing systems for testing electronic equipment
A testing method for testing a plurality of devices under test (DUT) includes transmitting first testing routine signals from a first backend controller to a...
US-1,010,2091 System and method for supporting a testing framework for an event processing system using multiple input event...
Systems and methods can use a testing framework for testing an event processing system. The testing framework operates to send a plurality of input events in...
US-1,010,2090 Non-destructive analysis to determine use history of processor
A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a...
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