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Patent # Description
US-1,013,4932 Solar cell and method of fabricating the same
A solar cell according to the embodiment includes a support substrate; a back electrode layer on the support substrate; a light absorbing layer on the back...
US-1,013,4931 Layer system for thin-film solar cells
The present invention relates to a layer system (1) for thin-film solar cells (100) and solar modules, comprising an absorber layer (4), which includes a...
US-1,013,4930 Solar cell having three-dimensional P-N junction structure and method for manufacturing same
The present invention provides a 3-dimensional P-N junction solar cell composed of a base board coated with a back plate on the upper face of the same; a P type...
US-1,013,4929 Achieving band gap grading of CZTS and CZTSe materials
Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se...
US-1,013,4928 Photoelectric conversion element and solar cell module provided with same
There is provided a photoelectric conversion element which includes an n-type single crystal silicon substrate (1). The n-type single crystal silicon substrate...
US-1,013,4927 Reliable electrical contacts for high power photoconductive switches
A photoconductive switch consisting of an optically actuated photoconductive material, e.g. a wide bandgap semiconductor such as SiC, situated between opposing...
US-1,013,4926 Quantum-efficiency-enhanced time-of-flight detector
A time-of-flight detector includes a semiconductor layer and a light modulation structure. The semiconductor layer is configured to translate light radiation...
US-1,013,4925 Conductive paste composition and semiconductor devices made therewith
The present invention provides a thick-film paste composition for printing the front side of a solar cell device having one or more insulating layers. The...
US-1,013,4924 Screen-printing system for a photovoltaic cell, and related methods
Screen-printing system comprising a metal stencil (12), and a cloth (15) fixed to the entire periphery of said metal stencil (12) to form a trampoline assembly,...
US-1,013,4923 Photovoltaic devices including bi-layer pixels having reflective and/or antireflective properties
PV devices including bi-layer pixels having reflective and/or antireflective properties, and methods for manufacturing PV devices including bi-layer pixels...
US-1,013,4922 Window structure, method of manufacturing the same, electronic device equipped with a camera including a window...
A window structure includes a window, a design layer structure on the window, a light shield layer on the design layer structure, and a light absorption layer....
US-1,013,4921 Semiconductor device
A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second...
US-1,013,4920 Silicon carbide semiconductor device
A mesa type p-n junction diode silicon carbide semiconductor device that includes a first silicon carbide semiconductor substrate, a first drift layer formed on...
US-1,013,4919 Method of forming vertical flash memory
A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a...
US-1,013,4918 Memory device and method for fabricating the same
A method includes patterning a substrate to form a nanowire over the substrate, applying a plurality of doping processes to the nanowire to form a first...
US-1,013,4917 Tight pitch vertical transistor EEPROM
A memory device including a first conductivity type vertically orientated semiconductor device in a first region of a substrate and a second conductivity type...
US-1,013,4916 Transistor devices, memory cells, and arrays of memory cells
A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate...
US-1,013,4915 2-D material transistor with vertical structure
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor...
US-1,013,4914 Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide...
US-1,013,4913 Method of manufacturing amorphous IGZO TFT-based transient semiconductor
Disclosed is a method of manufacturing an a-IGZO TFT-based transient semiconductor. The method includes (a) stacking a thermal oxide layer on a silicon...
US-1,013,4912 Display device and electronic device
A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is...
US-1,013,4911 Semiconductor device
A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is...
US-1,013,4910 Semiconductor device and production method therefor
A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal...
US-1,013,4909 Semiconductor device and method for manufacturing the same
In order to form a structure in which an oxide semiconductor layer through which a carrier flows is not in contact with a gate insulating film, a buried channel...
US-1,013,4908 Semiconductor device and manufacturing method thereof
A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a...
US-1,013,4907 Low temperature polysilicon array substrate and method for manufacturing the same
Disclosed is a low temperature polysilicon array substrate and its manufacturing method. The method includes: forming a light-shielding layer, a buffer layer...
US-1,013,4906 Display device
According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second...
US-1,013,4905 Semiconductor device including wrap around contact, and method of forming the semiconductor device
A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on...
US-1,013,4904 Semiconductor device having a flexible substrate and a crack-preventing semiconductor layer
Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display...
US-1,013,4903 Vertical slit transistor with optimized AC performance
A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed...
US-1,013,4902 PMOS FinFET
A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process...
US-1,013,4901 Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the...
Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the...
US-1,013,4900 SiGe source/drain structure and preparation method thereof
A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal...
US-1,013,4899 Facet-free strained silicon transistor
The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material...
US-1,013,4898 High dose implantation for ultrathin semiconductor-on-insulator substrates
Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant...
US-1,013,4897 Semiconductor device and fabrication method thereof
A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess...
US-1,013,4896 Cyclic deposition etch chemical vapor deposition epitaxy to reduce EPI abnormality
A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure...
US-1,013,4895 Facet-free strained silicon transistor
The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material...
US-1,013,4894 Dual gate FD-SOI transistor
Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology....
US-1,013,4893 Fabrication of a vertical field effect transistor device with a modified vertical fin geometry
A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a...
US-1,013,4892 High voltage device with low R.sub.dson
High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The...
US-1,013,4891 Transistor device with threshold voltage adjusted by body effect
A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is...
US-1,013,4890 Termination region architecture for vertical power transistors
A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures...
US-1,013,4889 Compound semiconductor device and method of manufacturing the compound semiconductor device
A disclosed compound semiconductor device includes a substrate, a channel layer formed over the substrate, an electron supply layer famed on the channel layer,...
US-1,013,4888 Semiconductor device and method of manufacturing the same
A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the...
US-1,013,4887 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a...
US-1,013,4886 Insulated gate bipolar device and manufacturing method thereof
In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material...
US-1,013,4885 Semiconductor device having an active trench and a body trench
A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main...
US-1,013,4883 Electronic device using group III nitride semiconductor and its fabrication method
The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and...
US-1,013,4882 Method of junction control for lateral bipolar junction transistor
A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon...
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