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Patent # Description
US-1,013,4881 Quantum well thermal sensing for power amplifier
A heterojunction bipolar transistor (HBT) thermal sensing device includes a well structure as a layer between an HBT sub-collector and an HBT substrate. In one...
US-1,013,4880 Self-aligned bipolar junction transistors with a base grown in a dielectric cavity
Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a...
US-1,013,4879 Semiconductor device and method for fabricating the same
The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided....
US-1,013,4878 Oxygen vacancy of IGZO passivation by fluorine treatment
Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide...
US-1,013,4877 Organic light emitting diode display having thin film transistor substrate using oxide semiconductor
A method for manufacturing an organic light emitting diode (OLED) display can include forming a gate electrode on a substrate, forming a semiconductor layer by...
US-1,013,4876 FinFETs with strained channels and reduced on state resistance
The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances...
US-1,013,4875 Method for fabricating a transistor having a vertical channel having nano layers
The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second...
US-1,013,4874 Vertical field effect transistors with bottom source/drain epitaxy
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first...
US-1,013,4873 Semiconductor device gate structure and method of fabricating thereof
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer...
US-1,013,4872 Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating...
US-1,013,4871 Doping of high-K dielectric oxide by wet chemical treatment
A method for fabricating a semiconductor device includes forming a first high-k (HK) dielectric layer over a substrate, performing a wet treatment process to...
US-1,013,4870 Semiconductor structure and method of manufacturing the same
A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a...
US-1,013,4869 Method of manufacturing semiconductor device
To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is...
US-1,013,4868 MOS devices with mask layers and methods for forming the same
A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are...
US-1,013,4867 Method for fabricating semiconductor device
A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is...
US-1,013,4866 Field effect transistor air-gap spacers with an etch-stop layer
Provided herewith are embodiments related to a semiconductor structure and a method for forming the semiconductor structure. A first spacer layer and a second...
US-1,013,4865 One-dimensional nanostructure growth on graphene and devices thereof
A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of...
US-1,013,4864 Nanowire semiconductor device including lateral-etch barrier region
A semiconductor device includes a semiconductor-on-insulator wafer having a buried layer. The buried layer includes therein opposing etch barrier regions and a...
US-1,013,4863 Vertical semiconductor device structure and method of forming
Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel...
US-1,013,4862 Semiconductor device containing fin and back gate and method for manufacturing the same
High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate;...
US-1,013,4861 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed...
US-1,013,4860 Semiconductor device having a dielectric layer with different thicknesses and method for forming
A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well...
US-1,013,4859 Transistor with asymmetric spacers
A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance...
US-1,013,4858 Semiconductor having isolated gate structure
A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer...
US-1,013,4857 Semiconductor device
The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon...
US-1,013,4856 Semiconductor device including contact plug and method of manufacturing the same
A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain...
US-1,013,4855 Thin film transistor substrate
A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and...
US-1,013,4854 High electron mobility transistor and fabrication method thereof
A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through...
US-1,013,4853 Method of manufacturing a semiconductor device having an impurity concentration
A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body,...
US-1,013,4852 Semiconductor device
In a transistor including an oxide semiconductor film, movement of hydrogen and nitrogen to the oxide semiconductor film is suppressed. Further, in a...
US-1,013,4851 Tunnel barrier schottky
A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded...
US-1,013,4850 Semiconductor device
A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate...
US-1,013,4849 Semiconductor device and manufacturing method thereof
The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor....
US-1,013,4848 Semiconductor device having a graphene layer, and method of manufacturing thereof
A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide...
US-1,013,4847 FinFET structures and methods of forming the same
FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain...
US-1,013,4846 Semiconductor device
A semiconductor device including a semiconductor substrate having an edge termination portion and an active portion is provided. The edge termination portion...
US-1,013,4845 Method and power semiconductor device having an insulating region arranged in an edge termination region
A power semiconductor device includes a semiconductor body having first and second opposing sides and an edge termination region arranged between an active...
US-1,013,4844 Semiconductor device including fin structures disposed over buffer structures
A semiconductor FET device includes a buffer structure and a fin structure. The buffer structure has a fin shape, is disposed over a substrate and extends along...
US-1,013,4843 Multi-gate device and method of fabrication thereof
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first...
US-1,013,4842 Heterojunction bipolar transistor
A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar...
US-1,013,4841 Nanowire semiconductor device structure and method of manufacturing
A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the...
US-1,013,4840 Series resistance reduction in vertically stacked silicon nanowire transistors
Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a...
US-1,013,4839 Field effect transistor structure having notched mesa
A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch...
US-1,013,4838 Semiconductor device
A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper...
US-1,013,4837 Porous silicon post processing
A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an...
US-1,013,4836 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are provide. The fabricating method includes providing a silicon-on-insulator (SOI) substrate that...
US-1,013,4835 Power semiconductor device having fully depleted channel regions
A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal...
US-1,013,4834 Field effect transistor devices with buried well protection regions
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first...
US-1,013,4833 Multiple work function device using GeOx/TiN cap on work function setting metal
A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a...
US-1,013,4832 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode...
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