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Patent # Description
US-1,013,4780 Display device and manufacturing method thereof
According to one embodiment, a display device includes a first substrate including a first insulative substrate, an outer peripheral wiring formed above the...
US-1,013,4779 Display device having short circuit prevention pattern
A display device including a substrate including a bending area arranged between a first area and a second area, the substrate being configured to be bent...
US-1,013,4778 Array substrate and manufacturing method thereof, display panel and display device
A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each...
US-1,013,4777 Thin film transistor substrate and display device including the same
Disclosed is a thin film transistor substrate capable of preventing a circuit from being damaged by static electricity, and a display device including the same,...
US-1,013,4776 Display substrate and method of repairing defects thereof
A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line...
US-1,013,4775 Display device
By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case...
US-1,013,4774 Display device
A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the...
US-1,013,4773 Display device and manufacturing method thereof
A display device including a substrate including a display area for displaying an image and a non-display area provided on a side of the display area and...
US-1,013,4772 Array substrate, display panel and display apparatus
The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate includes gate lines and data lines defining a...
US-1,013,4771 Array substrate, method of producing array substrate, and display panel
An array substrate, a method of producing the array substrate, and a display panel incorporating the array substrate are disclosed. The array substrate includes...
US-1,013,4770 Preparation method of conductive via hole structure, array substrate and display device
A preparation method of a conductive via hole structure, a preparation method of an array substrate and a preparation method of a display device, the...
US-1,013,4769 Array substrate, method for manufacturing thereof, and display device
Disclosed is an array substrate, a method for manufacturing the same, and a display device. The array substrate includes: a base substrate and a plurality of...
US-1,013,4766 Semiconductor device and method for manufacturing the same
The number of photolithography steps used for manufacturing a transistor is reduced to less than the conventional one and a highly reliable semiconductor device...
US-1,013,4765 Oxide semiconductor TFT array substrate and method for manufacturing the same
A method for manufacturing an oxide semiconductor TFT array substrate is provided, which including: successively depositing an oxide semiconductor active layer...
US-1,013,4764 Flexible substrate and manufacturing method thereof, flexible display panel and flexible display device
The invention provide a flexible substrate and manufacturing method thereof, flexible display panel and flexible display device, wherein the flexible substrate...
US-1,013,4763 Gate top spacer for finFET
The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the...
US-1,013,4762 Embedded security circuit formed by directed self-assembly
Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set...
US-1,013,4761 Semiconductor device and FinFET transistor
The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor...
US-1,013,4760 FinFETs with various fin height
A device and method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation...
US-1,013,4759 Semiconductor device including groups of nanowires of different semiconductor materials and related methods
A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a...
US-1,013,4758 Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
US-1,013,4757 Method of processing a substrate and a device manufactured by using the method
A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure...
US-1,013,4756 Semiconductor device
A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad...
US-1,013,4755 Semiconductor memory device
A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending...
US-1,013,4754 Method for forming a 3-D memory device and the 3-D memory device formed thereby
A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array...
US-1,013,4753 Vertical memory devices
According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance...
US-1,013,4752 Memory device
A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode...
US-1,013,4751 Non-volatile semiconductor memory device and manufacturing method thereof
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a...
US-1,013,4750 Stacked type semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first...
US-1,013,4749 Semiconductor memory device
A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first...
US-1,013,4748 Cell boundary structure for embedded memory
Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In...
US-1,013,4747 Semiconductor device and method of manufacturing the same
A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a...
US-1,013,4746 Self aligned active trench contact
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill...
US-1,013,4745 Conductive layers with different thicknesses
A semiconductor chip includes: a first conductive line formed in a first conductive layer, a second conductive line formed in a second conductive layer, and a...
US-1,013,4744 Semiconductor memory device
A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access...
US-1,013,4743 Structure and method for statice random access memory device of vertical tunneling field effect transistor
Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least...
US-1,013,4742 Semiconductor device including a semiconductor substrate, a pillar, and a beam
The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion...
US-1,013,4741 Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from...
US-1,013,4740 Semiconductor device and method for fabricating the same
A semiconductor device including a substrate; a trench formed within the substrate; a gate insulating film formed conformally along a portion of a surface of...
US-1,013,4739 Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of...
Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and...
US-1,013,4738 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-1,013,4737 Memory device with reduced-resistance interconnect
An interconnect structure includes a lower interconnect layer, an intermediate interconnect layer, and an upper interconnect layer. First and second conductive...
US-1,013,4736 Method of integrating thyristor and metal-oxide semiconductor transistor on a semiconductor substrate
A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first...
US-1,013,4735 Heterogeneously integrated semiconductor device and manufacturing method thereof
A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a...
US-1,013,4734 Fin field effect transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits employing...
Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased...
US-1,013,4733 Semiconductor device
A semiconductor device includes a semiconductor substrate and a control electrode provided on a first surface side of the semiconductor substrate. The...
US-1,013,4732 Reduction of negative bias temperature instability
A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect...
US-1,013,4731 Dielectric liner added after contact etch before silicide formation
A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon,...
US-1,013,4730 FinFET device with enlarged channel regions
A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the...
US-1,013,4728 ESD centric low-cost IO layout design topology
An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated...
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