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Patent # Description
US-1,013,4727 High breakdown voltage III-N depletion mode MOS capacitors
III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to...
US-1,013,4726 Diode string implementation for electrostatic discharge protection
A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the...
US-1,013,4725 Electrostatic discharge protection circuit applied in integrated circuit
The present application provides an electrostatic discharge protection circuit including a first N-type transistor, a second N-type transistor and a...
US-1,013,4724 Electro-static discharge protection devices having a low trigger voltage
An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode...
US-1,013,4723 Electrostatic discharge protection device and electronic device having the same
In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each...
US-1,013,4722 Embedded PMOS-trigger silicon controlled rectifier (SCR) with suppression rings for electro-static-discharge...
An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with...
US-1,013,4721 Variable holding voltage silicon controlled rectifier using separate and distinct bipolars
A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of...
US-1,013,4720 Package including a plurality of stacked semiconductor devices having area efficient ESD protection
A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias--TSV) that can...
US-1,013,4719 Semiconductor package and manufacturing method thereof
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least...
US-1,013,4718 Power semiconductor module
A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive...
US-1,013,4717 Semiconductor package, semiconductor device and method of forming the same
According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component...
US-1,013,4716 Multi-package integrated circuit assembly with through-mold via
A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first...
US-1,013,4715 Display apparatus and methods
A display includes a plurality of pixel chips, chixels, provided on a substrate. The chixels and the light emitters thereon may be shaped, sized and arranged to...
US-1,013,4714 Flexible circuit board for LED lighting fixtures
Techniques are disclosed for making a flexible laminated circuit board using a metal conductor onto which a SMD may be attached. Conductive metal strips may be...
US-1,013,4713 Semiconductor package
A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first...
US-1,013,4712 Methods and systems for improving power delivery and signaling in stacked semiconductor devices
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the...
US-1,013,4711 Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same
A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring...
US-1,013,4710 Semiconductor package
A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element...
US-1,013,4709 Substrateless light emitting diode (LED) package for size shrinking and increased resolution of display device
A light emitting diode package including a circuit layer, a light-shielding layer, a plurality of light emitting diodes and an encapsulation layer is provided....
US-1,013,4708 Package with thinned substrate
A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an...
US-1,013,4707 Bonding method for connecting two wafers
The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a...
US-1,013,4706 Warpage control of semiconductor die package
Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the...
US-1,013,4705 Method of manufacturing semiconductor device
As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device...
US-1,013,4704 Thermocompression for semiconductor chip assembly
An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the...
US-1,013,4703 Package on-package process for applying molding compound
A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical...
US-1,013,4702 Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip
The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the...
US-1,013,4701 Solder bump for ball grid array
A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer....
US-1,013,4700 Via structure for packaging and a method of forming
A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying...
US-1,013,4699 Packages with solder ball revealed through layer
An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a...
US-1,013,4698 Bonding pad structure, bonding ring structure, and MEMS device packaging method
The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a...
US-1,013,4697 Semiconductor chip and method of processing a semiconductor chip
Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a...
US-1,013,4696 Spoked solder pad to improve solderability and self-alignment of integrated circuit packages
A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated...
US-1,013,4695 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
US-1,013,4694 Method of forming redistribution layer
A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed...
US-1,013,4693 Printed wiring board
A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on first surface of the lowermost layer, a conductor post...
US-1,013,4692 Body-mountable device with a common substrate for electronics and battery
An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or...
US-1,013,4691 Apparatus and method for generating identification key
An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second...
US-1,013,4690 Floating package stiffener
Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package...
US-1,013,4689 Warpage compensation metal for wafer level packaging technology
A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing...
US-1,013,4687 Semiconductor device and method of manufacturing a semiconductor device
An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield....
US-1,013,4686 Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components...
A compartment EMI shield is provided that is suitable for use in system module packages having thin form factors and/or smaller widths and/or lengths. The...
US-1,013,4685 Integrated circuit package and method of fabricating the same
An integrated circuit package including at least one integrated circuit component, at least one electromagnetic interference shielding layer and an insulating...
US-1,013,4684 Patterned shield structure
A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned...
US-1,013,4683 Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component,...
US-1,013,4682 Circuit package with segmented external shield to provide internal shielding between electronic components
A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic...
US-1,013,4681 Laser processing method for cutting semiconductor wafer having metal layer formed thereon and laser processing...
Disclosed are a laser processing method for cutting a semiconductor wafer having a metal layer formed thereon and a laser processing device. The disclosed laser...
US-1,013,4680 Electronic part embedded substrate and method of producing an electronic part embedded substrate
An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part,...
US-1,013,4679 Printed circuit board, package substrate comprising same, and method for manufacturing same
The printed circuit board, according to one embodiment, comprises: an insulation substrate; a pad formed on at least one side of the insulation substrate; a...
US-1,013,4678 Chip-on-film, flexible display panel and display device
The present disclosure provides a chip-on-film, a flexible display panel and a display device. The COF includes a plurality of output pads independent of each...
US-1,013,4677 Semiconductor package device and method of manufacturing the same
A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a...
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