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| Patent # | Description |
|---|---|
| US-1,013,4676 |
Flexible device having flexible interconnect layer using two-dimensional
materials A flexible device includes an electronic device having an electrode and a flexible interconnect layer formed on the electrode. The flexible interconnect layer... |
| US-1,013,4675 |
Cobalt top layer advanced metallization for interconnects An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes... |
| US-1,013,4674 |
Structure and method for improved stabilization of cobalt cap and/or
cobalt liner in interconnects A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate... |
| US-1,013,4673 |
Semiconductor device and manufacturing method thereof According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes... |
| US-1,013,4672 |
Semiconductor memory device having a stepped structure and contact wirings
formed thereon A semiconductor storage device includes a substrate, a stack of first insulating layers and conductive layers that are alternately formed on the substrate in a... |
| US-1,013,4671 |
3D interconnect multi-die inductors with through-substrate via cores A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)... |
| US-1,013,4670 |
Wafer with plated wires and method of fabricating same An aspect of the invention includes a method for plating wires on a wafer comprising: forming an array of integrated circuit (IC) chips having a redistribution... |
| US-1,013,4669 |
Method for forming fin field effect transistor (FinFET) device structure
with interconnect structure A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The... |
| US-1,013,4668 |
Package structure A package structure includes a lead frame, an insulator, a plurality of conductive vias, a patterned metal layer, and a chip. The lead frame includes a... |
| US-1,013,4667 |
Chip-on-film semiconductor packages and display apparatus including the
same Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF... |
| US-1,013,4666 |
Package substrate, method for fabricating the same, and package device
including the package substrate A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern... |
| US-1,013,4665 |
Semiconductor device A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a... |
| US-1,013,4664 |
Integrated circuit packaging system with embedded pad on layered substrate
and method of manufacture thereof An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the... |
| US-1,013,4663 |
Semiconductor device This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a... |
| US-1,013,4662 |
Mounting substrate and method of manufacturing the same A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming... |
| US-1,013,4661 |
Semiconductor device A semiconductor device comprises a first metal lead frame portion with a chip mounting surface, a second metal lead frame portion, and a semiconductor chip with... |
| US-1,013,4660 |
Semiconductor device having corrugated leads and method for forming A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated... |
| US-1,013,4659 |
Semiconductor device with overlapped lead terminals The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a... |
| US-1,013,4658 |
High power transistors High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than... |
| US-1,013,4657 |
Inorganic wafer having through-holes attached to semiconductor wafer A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer... |
| US-1,013,4656 |
Package integrated synthetic jet device Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling... |
| US-1,013,4655 |
Semiconductor device packages with direct electrical connections and
related methods Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An... |
| US-1,013,4654 |
Double-encapsulated power semiconductor module and method for producing
the same One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The... |
| US-1,013,4653 |
Semiconductor device having electrode pads arranged between groups of
external electrodes The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to... |
| US-1,013,4652 |
Substrate for integrated circuit package The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which... |
| US-1,013,4650 |
Apparatus and method for cutting a wafer that is substantially covered by
an opaque material A wafer cutting apparatus comprises a wafer positioning device for holding a wafer that is substantially covered with an opaque material such as molding... |
| US-1,013,4649 |
Scanning acoustic microscope sensor array for chip-packaging interaction
package reliability monitoring A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate;... |
| US-1,013,4648 |
Manufacturing method of semiconductor device Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening... |
| US-1,013,4647 |
Methods for forming interconnect assemblies with probed bond pads An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The... |
| US-1,013,4646 |
Display device and testing method thereof A display device and a testing method thereof are disclosed, in which a defect caused by an overflow of an organic film constituting an encapsulation film can... |
| US-1,013,4645 |
Stress monitoring device and method of manufacturing the same A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The... |
| US-1,013,4644 |
Method of manufacturing a semiconductor device having deep wells A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation... |
| US-1,013,4643 |
Poly gate extension design methodology to improve CMOS performance in dual
stress liner process flow An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and... |
| US-1,013,4642 |
Semiconductor device and method of forming the semiconductor device A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and... |
| US-1,013,4641 |
Enhanced integration of DMOS and CMOS semiconductor devices A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first... |
| US-1,013,4640 |
Semiconductor device structure with semiconductor wire A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base... |
| US-1,013,4639 |
Semiconductor structure having contact holes between sidewall spacers The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of... |
| US-1,013,4638 |
FETS and methods of forming FETS An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The... |
| US-1,013,4637 |
Method of forming a semiconductor component having multiple bipolar
transistors with different characteristics A semiconductor component is formed by providing a substrate having partially formed first and second transistors, a base electrode stack formed over the... |
| US-1,013,4636 |
Methods for producing semiconductor devices A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first... |
| US-1,013,4635 |
Stress relieving through-silicon vias Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped... |
| US-1,013,4633 |
Self-aligned contact with CMP stop layer In a self-aligned contact (SAC) process, a sacrificial etch stop layer is embedded over source/drain regions, i.e., directly over an interlayer dielectric (IDL)... |
| US-1,013,4632 |
Low-K dielectric layer and porogen A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The... |
| US-1,013,4631 |
Size-filtered multimetal structures A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in... |
| US-1,013,4630 |
Metal-graphene heterojunction metal interconnects, method of forming the
same, and semiconductor device... Disclosed herein are a metal-graphene heterojunction metal interconnect, a method of forming the same, and a semiconductor device including the same. The method... |
| US-1,013,4629 |
Method for manufacturing a semiconductor structure A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first... |
| US-1,013,4628 |
Multilayer structure including diffusion barrier layer and device
including the multilayer structure A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the... |
| US-1,013,4627 |
Silicon-on-plastic semiconductor device with interfacial adhesion layer A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over... |
| US-1,013,4626 |
Mechanisms for forming FinFETs with different fin heights A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure... |
| US-1,013,4625 |
Shallow trench isolation structure and fabricating method thereof In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The... |
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