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Patent # Description
US-1,013,3603 Computerized system for real-time resource transfer verification and tracking
A system for verifying resource transfers in real-time typically includes a classical computer apparatus and a quantum optimizer in communication with the...
US-1,013,3602 Adaptive contention-aware thread placement for parallel runtime systems
An adaptive contention-aware thread scheduler may place software threads for pairs of applications on the same socket of a multi-socket machine for execution in...
US-1,013,3601 Memory management
System and techniques for memory management are described herein. A request for an adjusted process-value for a process may be received. Here, the adjusted...
US-1,013,3600 Application load adaptive multi-stage parallel data processing architecture
Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared...
US-1,013,3599 Application load adaptive multi-stage parallel data processing architecture
Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared...
US-1,013,3598 Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to...
An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a...
US-1,013,3597 Intelligent GPU scheduling in a virtualization environment
Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a...
US-1,013,3596 System and method for supporting application interoperation in a transactional middleware environment
A system and method can support application interoperation in a transactional middleware environment. A first transaction server operates to initiate a global...
US-1,013,3595 Methods for producing task reminders on a device
Apparatuses, methods, and program products are disclosed for producing a task reminder on a device. One method includes detecting, by use of a processor, a task...
US-1,013,3594 Flexible physical function and virtual function mapping
Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.
US-1,013,3593 Virtual machine migration
Migrating servers from client networks to virtual machines (VMs) on a provider network. A migration appliance is installed or booted on the client network, and...
US-1,013,3592 Parallel processing of data
A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel...
US-1,013,3591 Network traffic data in virtualized environments
Approaches are described for collecting and/or utilizing network traffic information, such as network flow data, within a virtualized computing environment. The...
US-1,013,3590 Container runtime support
Processes, machines, and manufactures involving adaptable containers that can be built and torn down more efficiently than VMs, may support various processes,...
US-1,013,3589 Identifying help information based on application context
A system for presenting help information relating to a user of a computer program based on context of the computer program is provided. The system receives an...
US-1,013,3588 Transforming instructions for collaborative updates
In various example embodiments, a system and method for transforming instructions for collaborative updates are described herein. A group of instructions for an...
US-1,013,3587 Generating component pages to render in a configuration page in a graphical user interface to configure a...
Provided are a computer program product, system, and method for generating component pages to render in a configuration page in a graphical user interface (GUI)...
US-1,013,3586 Method to configure, control, and display data products from a user interface
The present invention relates to a method, system, or computer application that allows to define a product configuration and using this configuration, manage...
US-1,013,3585 Information processing apparatus including tags for controlling operation modes
Provided is an information processing apparatus including a decision unit configured to decide an operation mode defining an operation of a target apparatus on...
US-1,013,3584 Mechanism for obviating the need for host-side basic input/output system (BIOS) or boot serial peripheral...
The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium,...
US-1,013,3583 Electronic device, method for controlling electronic device, and program
There is provided an electronic device including a manipulation unit configured to acquire manipulation by a user, and a control unit configured to selectively...
US-1,013,3582 Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor
A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction...
US-1,013,3581 Linkable issue queue parallel execution slice for a processor
An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal...
US-1,013,3580 Apparatus and method to preclude load replays dependent on write combining memory space access in an...
An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if...
US-1,013,3579 Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if...
US-1,013,3578 System and method for an asynchronous processor with heterogeneous processors
Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a...
US-1,013,3577 Vector mask driven clock gating for power efficiency of a processor
A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform...
US-1,013,3576 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store...
US-1,013,3575 Instruction for performing a pseudorandom number generate operation
A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a...
US-1,013,3574 Power management of instruction processors in a system-on-a-chip
A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of...
US-1,013,3573 Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent...
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing a multivalue reduction using a parallel processing...
US-1,013,3572 Techniques for serialized execution in a SIMD processing system
A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active...
US-1,013,3571 Load-store unit with banked queue
A load-store unit having one or more banked queues is disclosed. In one embodiment, a load-store unit includes at least one queue that is subdivided into...
US-1,013,3570 Processors, methods, systems, and instructions to select and consolidate active data elements in a register...
A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a...
US-1,013,3569 Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and...
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction...
US-1,013,3568 Embedding code anchors in software documentation
Techniques are provided for performing automated operations to support the identification of software documentation in need of updating. Application screen...
US-1,013,3567 Systems and methods for pre-processing and runtime distribution of interactive content
Source interactive content is obtained, including asset objects and code objects. Interactive content metadata is generated from the source interactive content,...
US-1,013,3566 Software upgrading system and method in a distributed multi-node network environment
A software upgrade in a data communication network may be provided by a first node. The first node may transfer a software unit to other nodes in the network....
US-1,013,3565 System and method for context aware mobile application installation queuing
According to some embodiments, method for managing an application installation queue on a mobile device is described. The method may include evaluating...
US-1,013,3564 Application wrapping system and method
A method of administering a computing system, including a plurality of computing devices. The method includes selecting an application for inclusion in a menu...
US-1,013,3563 Deployed image monitoring and relevant change detection
As disclosed herein a method, executed by a computer, includes receiving, from a monitoring agent, a notification that an artifact corresponding to a deployed...
US-1,013,3562 Efficiently representing complex score models
Data is received that characterizes a score model. Thereafter, the score model is normalized by transforming it into a directed acyclic graph. The directed...
US-1,013,3561 Partial redundancy elimination with a fixed number of temporaries
A method for partial redundancy elimination with a fixed number of temporaries includes determining local data values of program code that describe a temporary...
US-1,013,3560 Link time program optimization in presence of a linker script
A method for optimizing source code comprises optimizing the source code of files from a computer program at link-time, and receiving, at a linker, a customized...
US-1,013,3559 Generating executable files through compiler optimization
Embodiments of the present invention may track a user's interaction trajectory associated with a problem occurred on a website. According to an embodiment of...
US-1,013,3558 Application creation system
A computer implemented method and system for creating a mobile application provides a mobile application development software (MADS) and pre-coded software...
US-1,013,3557 Modifying code to reduce redundant or unnecessary power usage
Disclosed herein are representative embodiments of methods, apparatus, and systems for analyzing and/or transforming code (typically, source code) to reduce or...
US-1,013,3556 Technical building block
A virtual technical building block software development tool and a software development interface that speed accurate and quality software design are provided....
US-1,013,3555 Method of operating random pulse generator apparatus using radioisotope
Provided is an operating method of a random pulse generation apparatus using radioactive isotopes. An operating method of a random pulse generation apparatus...
US-1,013,3554 Non-modular multiplier, method for non-modular multiplication and computational device
A non-modular multiplier, a method for non-modular multiplication and a computational device are provided. The non-modular multiplier includes an interface and...
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