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Patent # Description
US-1,014,1446 Formation of bottom junction in vertical FET devices
Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor...
US-1,014,1445 Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of...
US-1,014,1444 Oxide thin-film transistor with illuminated OHMIC contact layers, array substrate and methods for manufacturing...
An oxide thin-film transistor, an array substrate and methods for manufacturing the same, and a display device are provided. The method for manufacturing the...
US-1,014,1443 Semiconductor devices FinFET devices with optimized strained-sourece-drain recess profiles and methods of...
Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the...
US-1,014,1442 Semiconductor device having tipless epitaxial source/drain regions
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device...
US-1,014,1441 Vertical transistor with back bias and reduced parasitic capacitance
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the...
US-1,014,1440 Drift-region field control of an LDMOS transistor using biased shallow-trench field plates
Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete...
US-1,014,1439 Semiconductor device and method of manufacturing the same
A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor...
US-1,014,1438 Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V...
US-1,014,1437 Extreme high mobility CMOS logic
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS...
US-1,014,1436 Tunnel field effect transistor having anisotropic effective mass channel
A tunnel field effect transistor (TFET) includes a substrate, heavily doped source and drain regions disposed at opposite ends of a channel region forming a PiN...
US-1,014,1435 Electronic device using group III nitride semiconductor and its fabrication method
The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and...
US-1,014,1434 Complementary tunneling field effect transistor and manufacturing method therefor
A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that...
US-1,014,1433 Method of manufacturing thin film transistor
The present application discloses a method of manufacturing a thin film transistor, including following steps: forming a gate electrode on the top surface of...
US-1,014,1432 Semiconductor structure
A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy...
US-1,014,1431 Epitaxy source/drain regions of FinFETs and method forming same
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor...
US-1,014,1430 Fin structures with uniform threshold voltage distribution and method of making the same
The present disclosure provides a method of forming a semiconductor device structure. The method includes determining a threshold voltage distribution profile...
US-1,014,1429 FinFET having isolation structure and method of forming the same
A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over...
US-1,014,1428 Fin formation in fin field effect transistors
A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon...
US-1,014,1427 Methods of manufacturing semiconductor devices including gate pattern, multi-channel active pattern and...
A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a...
US-1,014,1426 Vertical transistor device
According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate,...
US-1,014,1425 Method for manufacturing semiconductor device
A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor...
US-1,014,1424 Method of producing a channel structure formed from a plurality of strained semiconductor bars
Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make...
US-1,014,1423 Thin film transistor and fabrication method thereof, array substrate and fabrication method thereof, display...
The disclosure provides a thin film transistor (TFT) and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display...
US-1,014,1422 Method of manufacturing a semiconductor device integrating a vertical conduction transistor, and semiconductor...
A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a...
US-1,014,1421 Vertical power MOSFET and methods of forming the same
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and...
US-1,014,1420 Transistors with dielectric-isolated source and drain regions
Semiconductor devices and method of forming the same include forming a sacrificial layer on source/drain regions of a semiconductor layer. A reactant layer is...
US-1,014,1419 Two-step dummy gate formation
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor...
US-1,014,1418 Device with heteroepitaxial structure made using a growth mask
A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is...
US-1,014,1417 Gate structure, semiconductor device and the method of forming semiconductor device
A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a...
US-1,014,1416 Semiconductor structure with enlarged gate electrode structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate....
US-1,014,1415 Combined gate and source trench formation and related structure
A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first...
US-1,014,1414 Negative capacitance matching in gate electrode structures
A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When...
US-1,014,1413 Wafer strength by control of uniformity of edge bulk micro defects
Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region....
US-1,014,1412 Field effect transistor using transition metal dichalcogenide and a method for manufacturing the same
A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode....
US-1,014,1411 Temperature sensing semiconductor device
A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion...
US-1,014,1410 Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle...
A semiconductor device according to an embodiment includes an n-type SiC region, an electrode in contact with the SiC region, and a region including oxygen, the...
US-1,014,1409 Thin film transistor and array substrate thereof each having doped oxidized or doped graphene active region and...
A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a...
US-1,014,1408 Method and arrangement for reducing contact resistance of two-dimensional crystal material
A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a...
US-1,014,1407 Graphene device and method of manufacturing the same
According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on...
US-1,014,1406 Tensile strained NFET and compressively strained PFET formed on strain relaxed buffer
A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A...
US-1,014,1405 Lateral bipolar junction transistor with abrupt junction and compound buried oxide
A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a...
US-1,014,1404 Power semiconductor device having fully depleted channel region
A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected...
US-1,014,1403 Integrating thin and thick gate dielectric nanosheet transistors on same chip
A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes forming a first stack of...
US-1,014,1402 FinFET devices
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
US-1,014,1401 Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first...
US-1,014,1400 Semiconductor devices including field effect transistors with dummy gates on isolation
A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a...
US-1,014,1399 Semiconductor device
According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second...
US-1,014,1398 High voltage MOS structure and its manufacturing method
A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and...
US-1,014,1397 Semiconductor device and method of manufacturing the same
A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each...
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