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Patent # Description
US-1,014,0252 Hardware node with matrix-vector multiply tiles for neural network processing
Hardware and methods for neural network processing are provided. A method in a system comprising a plurality of nodes, where each node comprises a plurality of...
US-1,014,0251 Processor and method for executing matrix multiplication operation on processor
A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an...
US-1,014,0250 Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture
Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2)...
US-1,014,0249 Approximate message passing with universal denoising
Various examples of methods and systems are provided for approximate message passing with universal denoising. In one example, a method includes applying an...
US-1,014,0248 Analog processor comprising quantum devices
Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a...
US-1,014,0247 Electronic device, reconfigurable processor and controlling methods thereof
Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one...
US-1,014,0246 Optimizing remote direct memory access (RDMA) with cache aligned operations
A system for optimizing remote direct memory accesses (RDMA) is provided. The system includes a first computing device and a second computing device disposed in...
US-1,014,0245 Memcached server functionality in a cluster of data processing nodes
A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed...
US-1,014,0244 Optical module and transmitting data in optical module
An optical module and a method of transmitting data in the optical module are provided in the present disclosure. According to an example, the optical module...
US-1,014,0243 Enhanced serial peripheral interface with hardware flow-control
Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting...
US-1,014,0242 General purpose input/output (GPIO) signal bridging with I3C bus interfaces and virtualization in a multi-node...
In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual...
US-1,014,0241 Data bus driving circuit, and semiconductor device and semiconductor memory device including the same
A semiconductor device includes a data processing unit that processes input data and outputs processed data, a logic inversion unit that receives the processed...
US-1,014,0240 Control messaging in multislot link layer flit
A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are...
US-1,014,0239 Superimposing butterfly network controls for pattern combinations
A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many ...
US-1,014,0238 Open compute project network card converted to PCIe riser
An Open Compute Project (OCP) mezzanine riser with repurposed connectivity to allow for increased PCIe card count on a motherboard server. The OCP mezzanine...
US-1,014,0237 Fail functional automated driving
A vehicle system includes a first communication path and a second communication path. The vehicle system further includes a processor programmed to determine a...
US-1,014,0236 Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting...
A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host...
US-1,014,0235 Server
A server includes a main board, a bridge board and sub boards. The bridge board is electrically connected to the main board and the sub boards. The main board...
US-1,014,0234 Storage apparatus and data access method
A storage apparatus includes a printed circuit board (PCB) and multiple memory chips symmetrically arranged on two sides of the PCB, where multiple memory chips...
US-1,014,0233 Mass storage device selector
A mass storage device selector (1000) operatively couplable between a host computer (12) and a plurality of mass storage devices (14), for allowing a user of...
US-1,014,0232 Peripheral component interface (PCI) system and method for expanding PCI nodes in an information handling system
An information handling system (IHS), peripheral component interface (PCI) system and method for expanding PCI nodes in an IHS. The PCI system includes a...
US-1,014,0231 Flexible port configuration based on interface coupling
Example embodiments disclosed herein relate to configuring a flexible port. The configuration of a computing device is detected based on a coupling of an...
US-1,014,0230 Communication system, communication system control method, and program
Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is...
US-1,014,0229 Wired communication with remote function calls
Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with...
US-1,014,0228 Real-time execution of MAC control logic
A method is provided for time accurate execution of MAC logic on a processor able to drive a radio interface. In a first step, a chain of commands is received...
US-1,014,0227 Reducing read transactions to peripheral devices
A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a...
US-1,014,0226 Control apparatus with load monitoring
A modular control apparatus, having a head module, and at least one supply module and peripheral module arranged on the head module and having a bus structure....
US-1,014,0225 Impedance adjustment in a memory device
Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the...
US-1,014,0224 Noise immune data path scheme for multi-bank memory architecture
In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory...
US-1,014,0223 System and method for odd modulus memory channel interleaving
A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC...
US-1,014,0222 Interface components
In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices...
US-1,014,0221 Method to handle host, device, and link's latency tolerant requirements over USB Type-C power delivery using...
A system and method for performing a latency tolerance operation, comprising: determining whether a host and a device coupled to a cable are both capable of...
US-1,014,0220 Method of performing authentication with a memory circuit using dynamic random access memory arrays
A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry...
US-1,014,0219 Multi-port shared cache apparatus
An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory....
US-1,014,0218 Non-uniform memory access support in a virtual environment
Methods, systems, and computer program products for configuring devices in a virtual environment are described. An example method includes determining a NUMA...
US-1,014,0217 Link consistency in a hierarchical TLB with concurrent table walks
The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a...
US-1,014,0216 Measuring address translation latency
An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address...
US-1,014,0215 Low overhead mapping for highly sequential data
Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics...
US-1,014,0214 Hypervisor translation bypass by host IOMMU with virtual machine migration support
A system and method of translation bypass includes a hypervisor configuring a host input-output memory management unit to translate a guest memory of a guest...
US-1,014,0213 Two level memory full line writes
A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near...
US-1,014,0212 Consistent and efficient mirroring of nonvolatile memory state in virtualized environments by remote mirroring...
Updates to nonvolatile memory pages are mirrored so that certain features of a computer system, such as live migration of applications, fault tolerance, and...
US-1,014,0211 Cache device and method for storing tag data and cache data in cache device
A cache device of an embodiment includes a tag/data memory. The tag/data memory includes a storage area capable of storing a plurality of pieces of tag data and...
US-1,014,0210 Method and apparatus for cache occupancy determination and instruction scheduling
An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on...
US-1,014,0209 Time de-interleaving circuit and time de-interleaving method for reducing a number of times of accessing memory
A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality...
US-1,014,0208 NUMA-aware garbage collection
System and Methods for non-uniform memory (NUMA) garbage collection are provided. Multiple memories and processors are categorized into local groups. A heap...
US-1,014,0207 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-1,014,0206 Computerized method and end-to-end "pilot as a service" system for controlling start-up/enterprise interactions
An end-to-end "pilot as service" system for software pilot testing, comprising a server including at least one processor and operative for generating a set of...
US-1,014,0205 Systems and methods for infrastructure validation
Systems and method are provided for testing an infrastructure. The infrastructure may include one or more computers connected by a network. Moreover, each of...
US-1,014,0204 Automated dynamic test case generation
Embodiments of the present invention provide systems and methods for generating a set of test cases using a base test program. The base test program may be used...
US-1,014,0203 Method and apparatus for dynamically analyzing the correctness of software
A method is provided for dynamically analyzing the correctness of software. A central processing unit of a target system has a trace interface that provides...
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