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Patent # Description
US-1,015,3394 Semiconductor structure
A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising...
US-1,015,3393 Light emitting diode of which an active area comprises layers of inn
A light emitting diode including an n-doped In.sub.XnGa.sub.(1-Xn)N layer and a p-doped In.sub.XpGa.sub.(1-Xp)N layer, and an active area arranged between the...
US-1,015,3391 Graphene display
A graphene display is provided. The graphene display includes a first graphene light-emitting unit and a second graphene light-emitting unit which are stacked...
US-1,015,3390 Bifacial solar cell
A bifacial solar cell includes a substrate; a first conductive type region having a conductive type different from a conductive type of the substrate; a first...
US-1,015,3389 Tellurate joining glass having processing temperatures less than or equal to 420.degree. C
The present invention relates to a glass, in particular a glass for the joining of glass panes for the production of vacuum insulating glasses at processing...
US-1,015,3388 Emissivity coating for space solar cell arrays
The present disclosure provides a solar cell array for deployment and use in a space environment, and methods of making same. The array includes a plurality of...
US-1,015,3387 Fabricating thin-film optoelectronic devices with added potassium
A method (200) and deposition zone apparatus (300) for fabricating thin-film optoelectronic devices (100), the method comprising: providing a...
US-1,015,3386 Photovaltaic device conducting layer
A multilayered structure may include a doped buffer layer on a transparent conductive oxide layer.
US-1,015,3385 Back contact type solar battery cell
A back contact type solar battery which provides a reduced electric power loss, free positioning of a bus bar, and a simple manufacturing process. The solar...
US-1,015,3384 Solderable contact regions
A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the...
US-1,015,3383 Solar string power point optimization
An apparatus and method that controls the power produced by a string of solar cells, enabling the string to operate at its maximum power point when connected to...
US-1,015,3382 Mechanical memory transistor
A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source...
US-1,015,3381 Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate
In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a...
US-1,015,3380 Semiconductor device
As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal...
US-1,015,3379 Thin-film transistor and manufacturing method thereof
The present invention provides a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor according to the...
US-1,015,3378 Semiconductor device comprising oxide semiconductor
Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure...
US-1,015,3377 Dual-gate thin film transistor and manufacturing method thereof and array substrate
The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes:...
US-1,015,3376 Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device
A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a...
US-1,015,3375 Semiconductor device and method for manufacturing semiconductor device
A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and...
US-1,015,3374 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present...
US-1,015,3373 FinFET device and method of forming
A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the...
US-1,015,3372 High mobility strained channels for fin-based NMOS transistors
Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc),...
US-1,015,3371 Semiconductor device with fins including sidewall recesses
A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first...
US-1,015,3370 Fin-type field effect transistor structure and manufacturing method thereof
A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The...
US-1,015,3369 Semiconductor structure with inverted U-shaped cap layer
The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate...
US-1,015,3368 Unipolar complementary logic
A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field...
US-1,015,3367 Gate length controlled vertical FETs
A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second...
US-1,015,3366 LDMOS transistor with lightly-doped annular RESURF periphery
Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions....
US-1,015,3365 Semiconductor device and a method of making a semiconductor device
A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of...
US-1,015,3364 Power module having a switch module for supporting high current densities
A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch...
US-1,015,3363 Transistor having high electron mobility and method of its manufacture
A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an AlGaN/GaN...
US-1,015,3362 Semiconductor device
In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a...
US-1,015,3361 Heterojunction bipolar transistor device integration schemes on a same wafer
The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on...
US-1,015,3360 Semiconductor device and method for manufacturing the same
A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric...
US-1,015,3359 Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least...
US-1,015,3358 Semiconductor device and method for manufacturing the same
A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the...
US-1,015,3357 Superjunction power semiconductor device and method for forming
A method for manufacturing a super junction power MOSFET includes forming a first trench in a substrate, forming a first oxide layer over the substrate and in...
US-1,015,3356 Method of manufacturing semiconductor device, and semiconductor device
A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type...
US-1,015,3355 Semiconductor mixed gate structure
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a...
US-1,015,3354 TFT substrate manufacturing method
The present invention provides a TFT substrate manufacturing method, which includes first forming a graphene semiconductor active layer on a metal foil, then...
US-1,015,3353 Semiconductor structure
The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer...
US-1,015,3352 Semiconductor device
A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of...
US-1,015,3351 Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a...
US-1,015,3350 Semiconductor device
The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom...
US-1,015,3349 Methods and structures for a split gate memory cell structure
A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion...
US-1,015,3348 Memory configurations
In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control...
US-1,015,3347 Semiconductor device, power supply circuit, computer, and method of manufacturing semiconductor device
A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride...
US-1,015,3346 Semiconductor device and method for manufacturing the same
To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a...
US-1,015,3345 Insulated gate switching device and method for manufacturing the same
A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor...
US-1,015,3344 Formation of dislocations in source and drain regions of FinFET devices
Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and...
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