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| Patent # | Description |
|---|---|
| US-1,015,3241 |
Semiconductor device and method of manufacturing the same A semiconductor device is provided. The semiconductor device includes an electrode pad provided above a semiconductor substrate; and a wire bonded on the... |
| US-1,015,3240 |
Method of packaging semiconductor devices Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise... |
| US-1,015,3239 |
Antennas and waveguides in InFO structures A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with... |
| US-1,015,3238 |
Electrical channel including pattern voids A channel to be coupled to an input of a receiver, the channel including: a first transmission line including: a first trace; and a first reference plane... |
| US-1,015,3237 |
Chip package and method for forming the same A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a... |
| US-1,015,3236 |
Semiconductor device and power electronics apparatus A semiconductor device is provided, the semiconductor device having: a semiconductor chip; a wiring substrate which supports the semiconductor chip and is... |
| US-1,015,3235 |
Image sensor device and image sensor module comprising the same The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active... |
| US-1,015,3234 |
System in package An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a... |
| US-1,015,3233 |
Interconnect structure and fabricating method thereof An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The... |
| US-1,015,3232 |
Crack stop with overlapping vias A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a... |
| US-1,015,3231 |
Interconnect structure and fabrication method thereof An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top... |
| US-1,015,3230 |
Method of manufacturing a semiconductor device comprising a semiconductor
chip mounted over a metal plate... An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first... |
| US-1,015,3229 |
Method of manufacturing semiconductor products, corresponding
semiconductor product and device A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding... |
| US-1,015,3228 |
Semiconductor device A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface opposite to the first... |
| US-1,015,3227 |
Method for producing semiconductor device and semiconductor device A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending... |
| US-1,015,3226 |
Heat dissipating device A heat dissipating device including a base including a heat absorbing plate made of a metallic material and configured for an electronic product to be placed... |
| US-1,015,3225 |
Systems and methods for optimizing information handling system component
temperature for performance In accordance with embodiments of the present disclosure, an information handling system may include a plurality of information handling resources and a thermal... |
| US-1,015,3224 |
Backside spacer structures for improved thermal performance Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are... |
| US-1,015,3223 |
Thermally enhanced semiconductor package with thermal additive and process
for making the same The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a... |
| US-1,015,3222 |
Package structures and methods of forming the same An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a... |
| US-1,015,3221 |
Face down dual sided chip scale memory package A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides... |
| US-1,015,3220 |
Silicon package having electrical functionality by embedded passive
components A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a... |
| US-1,015,3219 |
Fan out wafer level package type semiconductor package and package on
package type semiconductor package... A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base... |
| US-1,015,3218 |
Semiconductor structure and manufacturing method thereof A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between... |
| US-1,015,3217 |
Plasma processing apparatus and plasma processing method A plasma processing apparatus including a processing chamber, a radio frequency power source, a monitoring unit, and a calculation unit is provided. In the... |
| US-1,015,3216 |
Manufacturing method of semiconductor device Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over amain surface of a semiconductor... |
| US-1,015,3215 |
Oven enclosure for optical components with integrated purge gas pre-heater A cartridge in an oven enclosure includes a pre-heating feature for an incoming purge gas before the purge gas enters the space around an optical component,... |
| US-1,015,3214 |
Patterning method and a method of fabricating a semiconductor device using
the same A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel... |
| US-1,015,3213 |
Process of forming an electronic device including a drift region, a sinker
region and a resurf region An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the... |
| US-1,015,3212 |
Semiconductor device including contact structure A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First... |
| US-1,015,3211 |
Methods, apparatus, and system for fabricating finFET devices with
increased breakdown voltage At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The... |
| US-1,015,3210 |
Semiconductor device and method for fabricating the same A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped... |
| US-1,015,3209 |
Insulating gate separation structure and methods of making same One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate... |
| US-1,015,3208 |
High frequency attenuator High-frequency thin film chip attenuators can include a substrate having a first side and a second side, a first portion coupled to the first side of the... |
| US-1,015,3207 |
Method for manufacturing a silicon carbide wafer using a susceptor having
draining openings An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting... |
| US-1,015,3206 |
Dicing method and laser processing apparatus According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a... |
| US-1,015,3205 |
Package with metal-insulator-metal capacitor and method of manufacturing
the same A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A... |
| US-1,015,3204 |
Wafer level packaging of reduced-height infrared detectors Systems and methods may be provided for generating reduced-height circuit packages such as infrared detector packages. An alignment and dicing system may... |
| US-1,015,3203 |
Methods for forming metal layers in openings and apparatus for forming
same A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts... |
| US-1,015,3202 |
Neutral atom beam nitridation for copper interconnect A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening... |
| US-1,015,3201 |
Method for making a dipole-based contact structure to reduce the
metal-semiconductor contact resistance in MOSFETs A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at... |
| US-1,015,3200 |
Methods of forming a nanostructured polymer material including block
copolymer materials Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods... |
| US-1,015,3199 |
Semiconductor device and fabrication method therefor A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming... |
| US-1,015,3198 |
Low-resistance contact plugs and method forming same A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a... |
| US-1,015,3197 |
Methods of forming one or more covered voids in a semiconductor substrate Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for... |
| US-1,015,3196 |
Arrays of cross-point memory structures Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and... |
| US-1,015,3195 |
Semiconductor constructions comprising dielectric material Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with... |
| US-1,015,3194 |
Array of gated devices and methods of forming an array of gated devices An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid... |
| US-1,015,3193 |
Integrated circuit for a stable electrical connection and manufacturing
method thereof An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an... |
| US-1,015,3192 |
Electrostatic chuck device An electrostatic chuck device according to the present invention includes: an electrostatic chuck portion having a placement surface on which a plate-like... |
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