Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,017,0639 3D memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional...
US-1,017,0637 Perfectly symmetric gate-all-around FET on suspended nanowire
A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of...
US-1,017,0636 Gate-to-bulk substrate isolation in gate-all-around devices
A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second...
US-1,017,0635 Semiconductor device, display device, display apparatus, and system
A semiconductor device includes a base; a gate electrode to which a gate voltage is applied; a source electrode and a drain electrode through which an electric...
US-1,017,0634 Wire-last gate-all-around nanowire FET
A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain...
US-1,017,0633 Method for manufacturing semiconductor device
A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the...
US-1,017,0632 Semiconductor device including oxide semiconductor layer
As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal...
US-1,017,0631 Manufacturing methods of oxide thin film transistors
The manufacturing method of oxide thin film transistors (TFTs) includes: providing a substrate and forming an oxide semiconductor active layer on the substrate;...
US-1,017,0630 Manufacturing method of semiconductor memory device
To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied....
US-1,017,0629 Field-effect transistor and the manufacturing method
A field-effect transistor and a manufacturing method thereof are provided. The method includes depositing a first insulating layer on a substrate; forming a...
US-1,017,0628 Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance...
A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the...
US-1,017,0627 Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height
A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a...
US-1,017,0626 Transistor panel having a good insulation property and a manufacturing method thereof
A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein...
US-1,017,0625 Method for manufacturing a compact OTP/MTP technology
Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate...
US-1,017,0624 Non-planar transistor
A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin...
US-1,017,0623 Method of fabricating semiconductor device
A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer...
US-1,017,0622 Semiconductor device including MOS transistor having silicided source/drain region and method of fabricating...
A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or...
US-1,017,0621 Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor
Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting...
US-1,017,0620 Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates
A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality...
US-1,017,0619 Vertical schottky contact FET
A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is...
US-1,017,0618 Vertical transistor with reduced gate-induced-drain-leakage current
A method of forming a vertical transport fin field effect transistor, including, forming a bottom source/drain layer at the surface of the substrate, forming...
US-1,017,0617 Vertical transport field effect transistors
The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of...
US-1,017,0616 Methods of forming a vertical transistor device
One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom...
US-1,017,0615 Semiconductor device including a lateral transistor
A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first...
US-1,017,0614 Method of forming a semiconductor device
A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a...
US-1,017,0613 Semiconductor device
A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer....
US-1,017,0612 Epitaxial buffer layers for group III-N transistors on silicon substrates
Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon...
US-1,017,0611 T-gate field effect transistor with non-linear channel layer and/or gate foot face
Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of...
US-1,017,0610 Pseudomorphic high electron mobility transistor with low contact resistance
In certain aspects, a pseudomorphic high electron mobility transistor (pHEMT) comprises a substrate layer, a bottom barrier layer on the substrate layer, a...
US-1,017,0609 Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET
A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain...
US-1,017,0608 Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET
A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain...
US-1,017,0607 Semiconductor device
A semiconductor device has a semiconductor substrate including a first conductivity-type drift layer, a second conductivity-type base layer disposed in a...
US-1,017,0606 Insulated gate bipolar transistor and diode
A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side...
US-1,017,0605 MOS-bipolar device
A clustered Insulated Gate Bipolar Transistor (CIGBT) comprising a drift region (24), a P region (20) formed within the n-type drift region, an N well region...
US-1,017,0604 Method for making a semiconductor device including a resonant tunneling diode with electron mean free path...
A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped...
US-1,017,0603 Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped...
US-1,017,0602 Semiconductor device with multiple HBTs having different emitter ballast resistances
The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast...
US-1,017,0601 Structure and formation method of semiconductor device with bipolar junction transistor
A semiconductor device structure is provided. The semiconductor device structure includes a collector element formed in or over a semiconductor substrate. The...
US-1,017,0600 Method for manufacturing semiconductor device
A manufacturing method of a semiconductor device including a step of forming a silicon layer over a formation substrate, a step of forming a resin layer over...
US-1,017,0599 Semiconductor device including insulating films with different thicknesses and method for manufacturing the...
In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor...
US-1,017,0598 Semiconductor device and method for manufacturing the same
An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen...
US-1,017,0597 Method for forming flash memory unit
A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate...
US-1,017,0596 Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch
A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a...
US-1,017,0595 Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch
A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a...
US-1,017,0594 Punch through stopper in bulk finFET device
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting...
US-1,017,0593 Threshold voltage modulation through channel length adjustment
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate,...
US-1,017,0592 Integrated circuit structure with substrate isolation and un-doped channel
The present disclosure provides a method of fabricating a nonplanar circuit device. The method includes receiving a substrate having a first semiconductor layer...
US-1,017,0591 Self-aligned finFET formation
A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions...
US-1,017,0590 Vertical field effect transistors with uniform threshold voltage
Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a...
US-1,017,0589 Vertical power MOSFET and methods for forming the same
A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.