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Patent # Description
US-1,017,0588 Method of forming vertical transport fin field effect transistor with high-K dielectric feature uniformity
A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a...
US-1,017,0587 Heterogeneous source drain region and extension region
A semiconductor structure includes a source drain region of a first material and an extension region of a second material. A semiconductor device fabrication...
US-1,017,0586 Unipolar spacer formation for finFETs
A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on...
US-1,017,0585 Semiconductor devices having equal thickness gate spacers
A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET...
US-1,017,0584 Nanosheet field effect transistors with partial inside spacers
A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer...
US-1,017,0583 Forming a gate contact in the active area
A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate...
US-1,017,0582 Uniform bottom spacer for vertical field effect transistor
A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor...
US-1,017,0581 FinFET with reduced parasitic capacitance
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed...
US-1,017,0580 Structure of GaN-based transistor and method of fabricating the same
A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer...
US-1,017,0579 Surface treatment and passivation for high electron mobility transistors
A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band...
US-1,017,0578 Through-substrate via power gating and delivery bipolar transistor
Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes...
US-1,017,0577 Vertical transport FETs having a gradient threshold voltage
Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold...
US-1,017,0576 Stable work function for narrow-pitch devices
A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the...
US-1,017,0575 Vertical transistors with buried metal silicide bottom contact
A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a...
US-1,017,0574 Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device...
US-1,017,0573 Semiconductor device and fabrication method thereof
A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface...
US-1,017,0572 Self-aligned dual trench device
A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed...
US-1,017,0571 Semiconductor device and manufacturing method thereof
A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer,...
US-1,017,0570 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal...
US-1,017,0569 Thin film transistor fabrication utlizing an interface layer on a metal electrode layer
Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal...
US-1,017,0568 High voltage laterally diffused MOSFET with buried field shield and method to fabricate same
A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the...
US-1,017,0567 High voltage laterally diffused MOSFET with buried field shield and method to fabricate same
A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the...
US-1,017,0566 Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and...
A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of...
US-1,017,0565 Imaging device, method for driving imaging device, and electronic device
An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a photoelectric conversion element, a first...
US-1,017,0564 Manufacturing method of semiconductor device and semiconductor device
Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor...
US-1,017,0563 Gallium nitride semiconductor device with improved termination scheme
This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area...
US-1,017,0562 Semiconductor device having a junction portion contacting a Schottky metal
A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum...
US-1,017,0561 Diamond semiconductor device
In one embodiment, a diamond semiconductor device includes a first diamond semiconductor layer of a first conductivity type which has a main surface, a second...
US-1,017,0560 Semiconductor devices with enhanced deterministic doping and related methods
A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers...
US-1,017,0559 Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method
An RC-IGBT includes a semiconductor body formed having a base region incorporating a field stop zone where the base region and the field stop zone are both...
US-1,017,0558 Localized and self-aligned punch through stopper doping for finFET
A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the...
US-1,017,0557 Thyristor with improved plasma spreading
There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by...
US-1,017,0556 Semiconductor device and method for manufacturing the same
A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the...
US-1,017,0555 Intermetallic doping film with diffusion in source/drain
A method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first...
US-1,017,0554 Semiconductor device and manufacturing method thereof
A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate...
US-1,017,0553 Shaped terminals for a bipolar junction transistor
Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the...
US-1,017,0552 Co-integration of silicon and silicon-germanium channels for nanosheet devices
Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a...
US-1,017,0551 Sidewall image transfer nanosheet
A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising...
US-1,017,0550 Stressed nanowire stack for field effect transistor
A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second...
US-1,017,0549 Strained stacked nanosheet FETs and/or quantum well stacked nanosheet
Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing...
US-1,017,0548 Integrated capacitors with nanosheet transistors
A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same...
US-1,017,0547 Nanodevice
A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one...
US-1,017,0546 Fully substrate-isolated FinFET transistor
Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during...
US-1,017,0545 Memory arrays
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
US-1,017,0544 Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region
An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation...
US-1,017,0543 Vertical fin field effect transistor with air gap spacers
A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain...
US-1,017,0542 Semiconductor device
A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate...
US-1,017,0541 Semiconductor device including a plurality of electrodes and supporters
A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends...
US-1,017,0540 Capacitors
Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between...
US-1,017,0539 Stacked capacitor with enhanced capacitance
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a stacked structure and contact vias. The stacked structure...
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