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Patent # Description
US-1,017,0486 Semiconductor storage device comprising peripheral circuit, shielding layer, and memory cell array
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array...
US-1,017,0485 Three-dimensional stacked junctionless channels for dense SRAM
A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked...
US-1,017,0484 Integrated circuit structure incorporating multiple gate-all-around field effect transistors having different...
In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a...
US-1,017,0483 Semiconductor device, static random access memory cell and manufacturing method of semiconductor device
A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and...
US-1,017,0482 Structure to prevent lateral epitaxial growth in semiconductor devices
A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of...
US-1,017,0481 Semiconductor memory device and method of forming the same
A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer...
US-1,017,0480 Methods for manufacturing a fin-based semiconductor device including a metal gate diffusion break structure...
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more...
US-1,017,0479 Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
A method of forming a fin field effect transistor (finFET) with a doped substrate region, including forming a plurality of vertical fins on a substrate, forming...
US-1,017,0478 Spacer for dual epi CMOS devices
Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first...
US-1,017,0477 Forming MOSFET structures with work function modification
A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region...
US-1,017,0476 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench;...
US-1,017,0475 Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon...
US-1,017,0474 Two dimension material fin sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls....
US-1,017,0473 Forming long channel FinFET with short channel vertical FinFET and related integrated circuit
A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain...
US-1,017,0472 Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another...
US-1,017,0471 Bulk fin formation with vertical fin sidewall profile
A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer,...
US-1,017,0470 Switching device
A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating...
US-1,017,0469 Vertical field-effect-transistors having multiple threshold voltages
Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold...
US-1,017,0468 Semiconductor structure and method of manufacturing the same
A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a...
US-1,017,0467 Three dimensional memory device and method for fabricating the same
A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The...
US-1,017,0466 Device having an active channel region
In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is...
US-1,017,0465 Co-fabrication of vertical diodes and fin field effect transistors on the same substrate
A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming...
US-1,017,0464 Compound semiconductor devices having buried resistors formed in buffer layer
Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a...
US-1,017,0463 Bipolar transistor compatible with vertical FET fabrication
Methods of forming integrated chips include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the...
US-1,017,0462 Display device
An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a...
US-1,017,0461 ESD hard backend structures in nanometer dimension
Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is...
US-1,017,0460 Voltage balanced stacked clamp
Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is...
US-1,017,0459 Methods for an ESD protection circuit including a floating ESD node
Methods to forming low trigger-voltage ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including a...
US-1,017,0458 Manufacturing method of package-on-package structure
A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure...
US-1,017,0457 COWOS structures and method of forming the same
Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The...
US-1,017,0456 Semiconductor packages including heat transferring blocks and methods of manufacturing the same
A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an...
US-1,017,0455 Light emitting device with buffer pads
A light emitting device includes a carrier, a plurality of light emitting diode chips and a plurality of buffer pads. Each light emitting diode chip includes a...
US-1,017,0454 Method and apparatus for direct transfer of semiconductor device die from a mapped wafer
A system for performing a direct transfer of a plurality of semiconductor die from a first substrate to a second substrate based on map data of the location of...
US-1,017,0453 Arrangement and method for generating mixed light
The invention relates to an arrangement for generating mixed light, which comprises three semiconductor chips, emitting in the blue spectral range, of three...
US-1,017,0452 Pixel unit structure and manufacturing method thereof
A pixel unit structure, as well as a manufacturing method thereof, is provided. The pixel unit structure includes a display medium module and an active...
US-1,017,0450 Method for bonding and interconnecting integrated circuit devices
A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded...
US-1,017,0449 Deformable closed-loop multi-layered microelectronic device
A deformable closed-loop multi-layered microelectronic device is provided. A top layer, a bottom layer and a middle layer of the microelectronic device each...
US-1,017,0448 Apparatus and method of power transmission sensing for stacked devices
Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit...
US-1,017,0447 Advanced chip to wafer stacking
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips,...
US-1,017,0446 Structures and methods to enable a full intermetallic interconnect
A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder...
US-1,017,0445 Method for electrical coupling and electric coupling arrangement
A method for electrically coupling a pad and a front face of a pillar, including shaping the front face pillar, the front face having at least partially a...
US-1,017,0444 Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package...
US-1,017,0443 Debonding chips from wafer
A debonding device includes a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and...
US-1,017,0442 Mount structure including two members that are bonded to each other with a bonding material layer having a...
A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer...
US-1,017,0441 Semiconductor structure and manufacturing method thereof
A semiconductor structure comprises: a substrate, an alignment mark, pillars, and a seal wall. The alignment mark is adjacent to a surface of the substrate. The...
US-1,017,0440 Semiconductor device and a method of manufacturing thereof
A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad, and a second bonding pad on a top surface of the...
US-1,017,0439 Chamfering for stress reduction on passivation layer
Devices are formed to have inner layers that have electronic devices, and an outer passivation layer. A patterned conductor is formed on a first surface of the...
US-1,017,0438 Static discharge system
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge...
US-1,017,0437 Via disguise to protect the security product from delayering and graphic design system (GDS) hacking and method...
A method of forming a stop layer to prevent dummy vias from connecting to a metal layer and the resulting device are provided. Embodiments include forming a...
US-1,017,0436 Flash memory device having flame resistant
The invention provides a flash memory device having flame resistant, which comprises a first shell, a first circuit board, and a first transmission interface....
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