Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,017,0435 Guard ring structure and method for forming the same
A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a...
US-1,017,0434 Warpage control in package-on-package structures
A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top...
US-1,017,0433 Insulated circuit board, power module and power unit
An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner...
US-1,017,0432 Semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a...
US-1,017,0431 Electronic circuit package
Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of...
US-1,017,0430 Integrated fan-out package and method of fabricating the same
An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure...
US-1,017,0429 Method for forming package structure including intermetallic compound
Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure...
US-1,017,0428 Cavity generation for embedded interconnect bridges utilizing temporary structures
Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes...
US-1,017,0427 Semiconductor device and method
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating...
US-1,017,0426 Manufacturing method of wiring structure and wiring structure
A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the carbon,...
US-1,017,0425 Microstructure of metal interconnect layer
A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are...
US-1,017,0424 Cobalt first layer advanced metallization for interconnects
A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features...
US-1,017,0423 Metal cap integration by local alloying
A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal...
US-1,017,0422 Power strap structure for high performance and low current density
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and...
US-1,017,0421 Logic semiconductor devices
A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical...
US-1,017,0420 Patterning approach for improved via landing profile
The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the...
US-1,017,0419 Biconvex low resistance metal wire
At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or...
US-1,017,0418 Backside device contact
A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle...
US-1,017,0417 Semiconductor structure
A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a...
US-1,017,0416 Selective blocking boundary placement for circuit locations requiring electromigration short-length
A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the...
US-1,017,0415 Semiconductor device, semiconductor integrated circuit, and load driving device
On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input...
US-1,017,0414 Semiconductor device and a method for fabricating the same
A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first...
US-1,017,0413 Semiconductor device having buried metal line and fabrication method of the same
A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is...
US-1,017,0412 Substrate-less stackable package with wire-bond interconnect
A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a...
US-1,017,0411 Airgap protection layer for via alignment
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first...
US-1,017,0410 Semiconductor package with core substrate having a through hole
A semiconductor package includes a frame having a through hole, an electronic component disposed in the through hole, a metal layer disposed on either one or...
US-1,017,0409 Package on package architecture and method for making
Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly...
US-1,017,0408 Memory circuits and routing of conductive layers thereof
A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar,...
US-1,017,0407 Electronic device and methods of providing and using electronic device
Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first...
US-1,017,0406 Trace/via hybrid structure and method of manufacture
A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure...
US-1,017,0405 Wiring substrate and semiconductor package
A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer...
US-1,017,0404 Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier...
US-1,017,0403 Ameliorated compound carrier board structure of flip-chip chip-scale package
An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the...
US-1,017,0402 Semiconductor device
A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite...
US-1,017,0401 Integrated power module
An integrated power module comprising a power board including at least one power switching device, a driver board including at least one driver for driving a...
US-1,017,0400 Multi-finger transistor and semiconductor device
A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or...
US-1,017,0399 Capped through-silicon-vias for 3D integrated circuits
The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a...
US-1,017,0398 Three-dimensional integrated circuit
Disclosed is a three-dimensional integrated circuit divided into a plurality of groups and capable of repairing failed through-silicon vias (TSVs). In...
US-1,017,0397 Semiconductor devices, via structures and methods for forming the same
A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a...
US-1,017,0396 Through via structure extending to metallization layer
The integrated circuit device disclosed herein includes a substrate, an interlevel dielectric layer disposed over the substrate, an intermetal dielectric layer...
US-1,017,0395 Semiconductor device and a manufacturing method of the semiconductor device
A semiconductor device including a semiconductor module 10A, a semiconductor module 10B that has a lower switching voltage threshold than the semiconductor...
US-1,017,0394 Semiconductor device
A semiconductor device includes a laminated substrate having a circuit board; a semiconductor chip fixed to the circuit board; a terminal having a leading end...
US-1,017,0392 Wafer level integration for embedded cooling
Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming...
US-1,017,0391 Backside initiated uniform heat sink loading
A backside initiated uniform heat sink loading system includes a system board assembly, a heat sink assembly, a loading plate, and a fastener. The system board...
US-1,017,0389 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-1,017,0388 Surface passivation having reduced interface defect density
Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect...
US-1,017,0387 Temporary bonding scheme
A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one...
US-1,017,0386 Electronic component package and method of manufacturing the same
An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on...
US-1,017,0385 Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP
A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed....
US-1,017,0384 Methods and apparatus providing a graded package for a semiconductor
Methods and apparatus providing a graded package for a semiconductor are disclosed. An example apparatus includes a die; and a graded package encapsulating the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.