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Patent # Description
US-1,017,0383 Semiconductor device
A semiconductor device includes: an insulating board; a circuit pattern disposed on the insulating board; a semiconductor chip connected to the circuit pattern;...
US-1,017,0382 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an...
US-1,017,0381 Semiconductor wafer and method of backside probe testing through opening in film frame
A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center...
US-1,017,0380 Array substrate and display device
An array substrate and a display device are provided. The array substrate includes a display region and a peripheral circuit region, wherein a first gate line,...
US-1,017,0379 Wafer processing system
Disclosed herein is a wafer processing system for processing wafers one at a time, the wafer processing system including: a plurality of trays each configured...
US-1,017,0378 Gate all-around semiconductor device and manufacturing method thereof
Semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire...
US-1,017,0377 Memory cell with recessed source/drain contacts to reduce capacitance
A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a plurality of gate structures, a spacer...
US-1,017,0376 Device and forming method thereof
A device includes a first vertical nanowire, a second vertical nanowire and a gate. The first vertical nanowire is disposed on a substrate, wherein the first...
US-1,017,0375 FinFET devices with unique fin shape and the fabrication thereof
A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a...
US-1,017,0374 Semiconductor device and method for manufacturing the same
A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k...
US-1,017,0373 Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme
A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers...
US-1,017,0372 FINFET CMOS with Si NFET and SiGe PFET
A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through...
US-1,017,0371 Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a...
US-1,017,0370 Contact resistance control in epitaxial structures of finFET
A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and...
US-1,017,0369 Semiconductor device and fabrication method thereof
A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench...
US-1,017,0367 Semiconductor device and method
In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and...
US-1,017,0366 Semiconductor device having dummy gates and method of fabricating the same
A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed...
US-1,017,0365 Wrap around silicide for FinFETs
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the...
US-1,017,0364 Stress memorization technique for strain coupling enhancement in bulk finFET device
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
US-1,017,0363 Semiconductor device and method of manufacturing the semiconductor device
An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive...
US-1,017,0362 Semiconductor memory device with bit line contact structure and method of forming the same
The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a...
US-1,017,0361 Thin film interconnects with large grains
The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit...
US-1,017,0360 Reflow enhancement layer for metallization structures
A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the...
US-1,017,0359 Diffusion barrier layer formation
A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to...
US-1,017,0358 Reducing contact resistance in vias for copper interconnects
A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one...
US-1,017,0357 SOI wafer manufacturing process and SOI wafer
Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a...
US-1,017,0356 SOI substrate and manufacturing method thereof
This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a...
US-1,017,0355 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first...
US-1,017,0354 Subtractive methods for creating dielectric isolation structures within open features
A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein,...
US-1,017,0353 Devices and methods for dynamically tunable biasing to backplates and wells
Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method...
US-1,017,0352 Manufacturing apparatus of semiconductor device, and manufacturing method of semiconductor device
A manufacturing apparatus includes a first supporting section to support a first tape section. The first tape section has a first surface facing away from the...
US-1,017,0351 Transferring apparatus and method for manufacturing an integrated circuit device
In one embodiment a transferring apparatus comprises a rail connected to a frame, a travelling part including a wheel that travels along the rail and a loading...
US-1,017,0350 Correlation between conductivity and pH measurements for KOH texturing solutions and additives
The variability of an etchant concentration in an immersion processes for treatment of semiconductor devices can be significantly lowered by continuously...
US-1,017,0349 Substrate treating apparatus
A substrate treating apparatus includes a plurality of solution treating units for performing solution treatment of substrates, and a plurality of individual...
US-1,017,0348 Production system for printing electronic devices
A printing production line system for an electronic device includes a transport chamber with a robot transport line in which a self-traveling robot transports a...
US-1,017,0347 Substrate processing system
A substrate processing system for performing a process with respect to a plurality of substrates includes an annular process chamber configured to accommodate...
US-1,017,0346 Resin sealing apparatus and resin sealing method
A lower mold has a bottom surface member and a side surface member. An upper end surface of the bottom surface member forms an inner bottom surface of a cavity...
US-1,017,0345 Substrate processing apparatus
Disclosed is a substrate processing apparatus that includes: a polishing table; an atomizer configured to spray a fluid to a polishing surface; a polishing...
US-1,017,0344 Washing device and washing method
A washing device includes: a plurality of spindles which holds a substrate and rotates the substrate about a central axis of the substrate as a rotary axis; and...
US-1,017,0343 Post-CMP cleaning apparatus and method with brush self-cleaning function
Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP...
US-1,017,0342 Flow controlled liner having spatially distributed gas passages
Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables...
US-1,017,0341 Release film as isolation film in package
A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an...
US-1,017,0340 Semiconductor structure
A semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a...
US-1,017,0339 Semiconductor structure and a manufacturing method thereof
A method of manufacturing a semiconductor structure includes providing a substrate and a chip disposed over the substrate; disposing the substrate over a first...
US-1,017,0338 Vertical nanoribbon array (VERNA) thermal interface materials with enhanced thermal transport properties
A thermal interface material (TIM) and method for manufacture is disclosed. A vertically aligned carbon nanotube (VACNT) array is formed on a substrate, then...
US-1,017,0337 Implant after through-silicon via (TSV) etch to getter mobile ions
A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the...
US-1,017,0336 Methods for anisotropic control of selective silicon removal
Embodiments of the present technology may include a method of etching. The method may include flowing a gas through a plasma to form plasma effluents. The...
US-1,017,0335 Chemical mechanical polishing method for cobalt
A process for chemical mechanical polishing a substrate containing cobalt and TiN to at least improve cobalt: TiN removal rate selectivity. The process includes...
US-1,017,0334 Reduction of dishing during chemical mechanical polish of gate structure
A semiconductor device includes a semiconductor substrate, a gate structure and at least one CMP resistant structure. The gate structure is over the...
US-1,017,0333 Guard ring structure of semiconductor arrangement
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement...
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