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Patent # Description
US-1,017,0332 FinFET thermal protection methods and related structures
A method and structure for protecting high-mobility materials from exposure to high temperature processes includes providing a substrate having at least one fin...
US-1,017,0331 Stacked nanowires
Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method...
US-1,017,0330 Method for recessing a carbon-doped layer of a semiconductor structure
Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of...
US-1,017,0329 Spacer formation for self-aligned multi-patterning technique
Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a...
US-1,017,0328 Semiconductor pattern having semiconductor structures of different lengths
The present disclosure provides a semiconductor pattern and a method for preparing the same. The semiconductor pattern includes a substrate, a plurality of...
US-1,017,0327 Fin density control of multigate devices through sidewall image transfer processes
Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a...
US-1,017,0326 Wafer element with an adjusted print resolution assist feature
A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device...
US-1,017,0325 Hardmask composition and method of forming pattern by using the hardmask composition
A hardmask composition may include a solvent and a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen or a...
US-1,017,0324 Technique to tune sidewall passivation deposition conformality for high aspect ratio cylinder etch
Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition...
US-1,017,0323 Technique to deposit metal-containing sidewall passivation for high aspect ratio cylinder etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor...
US-1,017,0322 Atomic layer deposition based process for contact barrier layer
Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a...
US-1,017,0321 Aluminum content control of TiAIN films
Described are methods of depositing a titanium aluminum nitride film on a substrate surface with a controlled amount of carbon. The methods include exposing a...
US-1,017,0320 Feature fill with multi-stage nucleation inhibition
Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some...
US-1,017,0319 Forming a contact for a tall fin transistor
A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the...
US-1,017,0318 Self-aligned contact and manufacturing method thereof
A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure....
US-1,017,0317 Self-protective layer formed on high-k dielectric layer
Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second...
US-1,017,0316 Controlling threshold voltage in nanosheet transistors
Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based...
US-1,017,0315 Semiconductor device having local buried oxide
There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one...
US-1,017,0314 Pulsed laser anneal process for transistor with partial melt of a raised source-drain
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack...
US-1,017,0313 Systems and methods for a tunable electromagnetic field apparatus to improve doping uniformity
Systems and methods for improving doping and/or deposition uniformity using a tunable electromagnetic field generation device are provided. In an exemplary...
US-1,017,0312 Semiconductor substrate and manufacturing method of the same
Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including...
US-1,017,0311 Method for handling thin brittle films
A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the...
US-1,017,0310 Method of forming patterned structure
A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process...
US-1,017,0309 Dummy pattern addition to improve CD uniformity
A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an...
US-1,017,0308 Fabricating semiconductor devices by cross-linking and removing portions of deposited HSQ
A method of manufacturing a semiconductor device comprises forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate, forming a cap layer on the...
US-1,017,0307 Method for patterning semiconductor device using masking layer
A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further...
US-1,017,0306 Method of double patterning lithography process using plurality of mandrels for integrated circuit applications
A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between...
US-1,017,0305 Selective film growth for bottom-up gap filling
A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a...
US-1,017,0304 Self-aligned nanotube structures
The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The...
US-1,017,0303 Group IIIA nitride growth system and method
A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template...
US-1,017,0302 Superlattice lateral bipolar junction transistor
A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of...
US-1,017,0301 Adhesion of polymers on silicon substrates
Embodiments are directed to a method and resulting structures for improving the adhesion of a polymer to the surface of a substrate. A substrate is formed and a...
US-1,017,0300 Protective film forming method
A protective film forming method is provided. In the method, an oxide film of either an organic metal compound or an organic metalloid compound is deposited on...
US-1,017,0299 Method to reduce trap-induced capacitance in interconnect dielectric barrier stack
The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method...
US-1,017,0298 High temperature silicon oxide atomic layer deposition technology
Processes for depositing SiO.sub.2 films on a wafer surface utilizing an aminosilane compound as a silicon precursor are described.
US-1,017,0297 Compositions and methods using same for flowable oxide deposition
Described herein are compositions or formulations for forming a film in a semiconductor deposition process, such as without limitation, a flowable chemical...
US-1,017,0296 TiN pull-back and cleaning composition
The present invention relates to a novel composition that may be used to control the etching rate of TIN with respect to W, and remove any residues from the...
US-1,017,0295 Flux residue cleaning system and method
A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber...
US-1,017,0294 Conductive structure, lighting fixture, and lighting fixture assembling method
A conductive structure comprising: a plurality of conductive devices; a first conductive spring sheet, comprising a first connecting point; and a second...
US-1,017,0293 Enhanced lighting ceramic metal-halide lamp assembly
An enhanced lighting ceramic metal-halide lamp assembly provides a ceramic metal-halide lamp that operates to illuminate at high temperatures, have an increased...
US-1,017,0292 Method and apparatus for injection of ions into an electrostatic ion trap
A method of injecting ions into an electrostatic trap, comprising: generating ions in an ion source; transporting the ions from the ion source to an ion store...
US-1,017,0291 Apparatus for on-line monitoring particle contamination in special gases
An apparatus for on-line monitoring particle contamination in special gas includes a single particle inductively coupled plasma mass spectrometry (sp-ICPMS) and...
US-1,017,0290 Systems and methods for grouping MS/MS transitions
A method for analyzing a sample includes identifying a plurality of precursors for analysis and grouping the precursors into two or more groups. The precursors...
US-1,017,0289 Phototube and method of making it
A phototube suitable for detecting a photon, comprising: an electron ejector configured for emitting electrons in response to an incident photon; a detector...
US-1,017,0288 Sputtering apparatus
There is provided a sputtering apparatus in which a holding body holding a substrate by facing a target in a processing chamber is covered by a deposition...
US-1,017,0287 Techniques for detecting micro-arcing occurring inside a semiconductor processing chamber
Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to...
US-1,017,0286 In-situ cleaning using hydrogen peroxide as co-gas to primary dopant or purge gas for minimizing carbon...
An ion source assembly and method is provided for improving ion implantation performance. The ion source assembly has an ion source chamber and a source gas...
US-1,017,0285 Method of operating semiconductor manufacturing apparatus and semiconductor devices
Some embodiments of the present disclosure provide a semiconductor manufacturing apparatus. The semiconductor manufacturing apparatus includes a chamber, a...
US-1,017,0284 Plasma processing method and plasma processing apparatus
A plasma processing method according to an aspect includes: preparing a plasma processing apparatus including: a chamber; a lower electrode; an upper electrode;...
US-1,017,0283 Focus ring for plasma processing apparatus
There is provided a focus ring formed without an adhesive that can suppress abnormal electric discharge and obtain uniform plasma environment in a...
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