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Patent # Description
US-1,016,9266 Adaptive buffering of data received from a sensor
In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is...
US-1,016,9265 Configurable input / output connector in a camera
A camera includes an input/out system and one or more input/output ports. The camera configures the pins of the input/output port according to a default pin...
US-1,016,9264 Implementing robust readback capture in a programmable integrated circuit
In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM)...
US-1,016,9263 Memory subsystem and computer system
A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests...
US-1,016,9262 Low-power clocking for a high-speed memory interface
Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a...
US-1,016,9261 Address layout over physical memory
An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can...
US-1,016,9260 Multiprocessor cache buffer management
In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for...
US-1,016,9259 Pattern-based service bus architecture using activity-oriented services
A pattern-based service bus includes a plurality of bus endpoints, a bus-hosted service, and a bus storage component. The plurality of bus endpoints interact...
US-1,016,9258 Memory system design using buffer(s) on a mother board
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a...
US-1,016,9257 Module based data transfer
A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the...
US-1,016,9255 Information-sharing device, method, and terminal device for sharing application information
There is provided an information-sharing device including, in a second device connected to a first device, an information obtaining unit which obtains, through...
US-1,016,9254 Increasing virtual-memory efficiencies
Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which...
US-1,016,9253 Cryptographic multi-shadowing with integrity verification
A virtual-machine-based system that may protect the privacy and integrity of application data, even in the event of a total operating system compromise. An...
US-1,016,9252 Configuring functional capabilities of a computer system
Provided is a method for configuring the functional capabilities of a computer system. The computer system may include a persistent memory and a replaceable...
US-1,016,9251 Limted execution of software on a processor
A method for limiting execution of an encrypted computer program on a secure processor includes executing a first set of instructions encoding a test for...
US-1,016,9250 Method and apparatus method and apparatus for controlling access to a hash-based disk
A method and apparatus for controlling access to a hash-based disk is provided, the disk comprising a storage object, the storage object comprising a set of...
US-1,016,9249 Adjusting active cache size based on cache usage
Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device...
US-1,016,9248 Determining cores to assign to cache hostile tasks
Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores....
US-1,016,9247 Direct memory access between an accelerator and a processor using a coherency adapter
Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to...
US-1,016,9246 Reducing metadata size in compressed memory systems of processor-based systems
Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2.sup.N...
US-1,016,9245 Latency by persisting data relationships in relation to corresponding data in persistent memory
A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a...
US-1,016,9244 Controlling access to pages in a memory in a computing device
The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse...
US-1,016,9243 Reducing over-purging of structures associated with address translation
A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation...
US-1,016,9242 Heterogeneous package in DIMM
A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the...
US-1,016,9241 Managing memory allocation between input/output adapter caches
A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is...
US-1,016,9240 Reducing memory access bandwidth based on prediction of memory request size
Systems and methods for managing memory access bandwidth include a spatial locality predictor. The spatial locality predictor includes a memory region table...
US-1,016,9239 Managing a prefetch queue based on priority indications of prefetch requests
A prefetch request having a priority assigned thereto is obtained, based on executing a prefetch instruction included within a program. Based on obtaining the...
US-1,016,9238 Memory access for exactly-once messaging
A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages...
US-1,016,9237 Identification of a computing device accessing a shared memory
A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having...
US-1,016,9236 Cache coherency
A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable...
US-1,016,9235 Methods of overriding a resource retry
In an embodiment, an apparatus includes control circuitry and a memory configured to store a plurality of access instructions. The control circuitry is...
US-1,016,9234 Translation lookaside buffer purging with concurrent cache updates
A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address...
US-1,016,9233 Translation lookaside buffer purging with concurrent cache updates
A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address...
US-1,016,9232 Associative and atomic write-back caching system and method for storage subsystem
In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache...
US-1,016,9231 Efficient and secure direct storage device sharing in virtualized environments
A method, system and computer program product are disclosed for direct storage device sharing in a virtualized environment. In an embodiment, the method...
US-1,016,9230 Method for access to all the cells of a memory area for purposes of writing or reading data blocks in said cells
A method for access to all cells in a memory area for purposes of writing or reading data blocks in the cells may include, for each access time (Ti with i=0 to...
US-1,016,9229 Protocols for expanding existing sites in a dispersed storage network
A dispersed storage and task network (DSTN) includes a site housing current distributed storage and task (DST) execution units. A determination is made to add...
US-1,016,9228 Multi-section garbage collection
The embodiments relate to a method for managing a garbage collection process. The method includes executing a garbage collection process on a memory block of...
US-1,016,9227 Memory controller and memory system including the same
An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an...
US-1,016,9226 Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
US-1,016,9225 Memory system and memory-control method with a programming status
A memory system with a programming status is provided. The memory includes at least one first memory, at least one second memory and a controller. Each of the...
US-1,016,9224 Data protecting method for preventing received data from losing, memory storage apparatus and memory control...
A data protecting method, a memory storage apparatus and a memory control circuit unit are provided. The method includes: determining whether a first procedure...
US-1,016,9223 Identifying commits associated with failed tests
Techniques for identifying a build commit that caused a test failure are provided. A build which includes a failed test may be identified. For each commit in...
US-1,016,9222 Apparatus and method for expanding the scope of systems management applications by runtime independence
An apparatus for automatic conversion of existing systems management software applications to run in multiple middleware runtime frameworks by automating the...
US-1,016,9221 Method and system for web-site testing
The current document is directed to methods and systems for testing web sites. In certain implementations of the methods and systems, a testing service collects...
US-1,016,9220 Prioritizing resiliency tests of microservices
Techniques for automated resiliency testing systems are provided. In one example, a computer-implemented method comprises traversing, by a system operatively...
US-1,016,9219 System and method to infer call stacks from minimal sampled profile data
Methods and systems for inferring call stacks in a program, such as a video game or simulation program, are described herein. The call stack data can be...
US-1,016,9218 Method for automatically validating data against a predefined data specification
A method for automatically validating data against a predefined data specification, includes: a) acquiring data to be validated (2), the data including a...
US-1,016,9217 System and method for test generation from software specification models that contain nonlinear arithmetic...
A computer-implemented system for generating test cases and/or test procedures to verify software having a nonlinear arithmetic constraint over a Real number...
US-1,016,9216 Simulating sensors
Simulating sensors can include hooking an application associated with sensory data and associating the sensory data with an automation instruction. Simulating...
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