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Patent # Description
US-1,020,5034 Optical module
An optical module includes: an avalanche photodiode; a power supply terminal; a self bias resistor connected between a cathode of the avalanche photodiode and...
US-1,020,5033 ESD protected semiconductor photomultiplier
The present disclosure relates to a semiconductor photomultiplier which comprises one or more microcells on a substrate having at least one terminal. At least...
US-1,020,5032 Semiconductor structure and method for making same
One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an opening within the...
US-1,020,5031 Semiconductor device having resistance voltage dividing circuit
All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type...
US-1,020,5030 Method for manufacturing semiconductor device
To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is...
US-1,020,5029 Thin film transistor, manufacturing method thereof, and display device
A TFT, a manufacturing method thereof, and a display device are provided. The TFT includes a semiconductor layer and an etch-stop layer merely covering a...
US-1,020,5028 Thin-film transistor, manufacturing method for the same, display panel
A thin-film transistor, a manufacturing for the same, and a display panel are provided. In the annealing process, the aluminum layer combines with oxygen ions...
US-1,020,5027 Coplanar double gate electrode oxide thin film transistor and manufacture method thereof
The present disclosure relates to a coplanar double gate electrode oxide thin film transistor, includes a substrate, a bottom gate electrode, a first gate...
US-1,020,5026 Thin film transistor having a composite metal gate layer
A thin film transistor includes a substrate, and, a source electrode, a drain electrode, a gate, a gate insulation layer and an active layer disposed on the...
US-1,020,5025 Methods to achieve strained channel finFET devices
Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect...
US-1,020,5024 Semiconductor structure having field plate and associated fabricating method
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a...
US-1,020,5023 Semiconductor device including multi-channel active patterns
A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including...
US-1,020,5022 Method of making a semiconductor device using spacers for source/drain confinement
A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a...
US-1,020,5021 Method of fabrication of a semiconductor substrate having at least a tensilely strained semiconductor portion
Method of fabrication of a semiconductor substrate including fabrication of a semiconducting layer such that a first part of the semiconducting layer comprises...
US-1,020,5020 Semiconductor device
A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding...
US-1,020,5019 Semiconductor device having a fin at a side of a semiconductor body
One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part...
US-1,020,5018 Planar double gate semiconductor device
Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel...
US-1,020,5017 Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal...
US-1,020,5016 Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element
A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed...
US-1,020,5015 Reduced gate charge field-effect transistor
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region,...
US-1,020,5014 Method and apparatus for power device with multiple doped regions
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source...
US-1,020,5013 Semiconductor switching element and method of manufacturing the same
A semiconductor switching element includes a first gate electrode and a second gate electrode. The first gate electrode is disposed, via a first gate insulating...
US-1,020,5012 Semiconductor device
Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of first trench portions formed at a front surface side of the...
US-1,020,5011 Method for forming a semiconductor device with implanted chalcogen atoms
Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a...
US-1,020,5010 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front...
US-1,020,5009 Superjunction semiconductor device and method of manufacturing the same
A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first...
US-1,020,5008 Manufacturing method of semiconductor device
Provided is a semiconductor device with favorable electrical characteristics. Provided is a semiconductor device with stable electrical characteristics....
US-1,020,5007 Separation method and manufacturing method of flexible device
A low-cost separation method with high mass productivity is provided. A first layer with a thickness of 0.1 .mu.m or more and 3 .mu.m or less can be formed by...
US-1,020,5006 Method for manufacturing semiconductor device including patterning conductor film disposed on insulating film
A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area...
US-1,020,5005 Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first...
US-1,020,5004 FinFET isolation structure and method for fabricating the same
A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate and a fin isolation structure on the...
US-1,020,5003 Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers
A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate;...
US-1,020,5002 Method of epitaxial growth shape control for CMOS applications
The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more...
US-1,020,5001 Hybrid active-field gap extended drain MOS transistor
An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended...
US-1,020,5000 Semiconductor device with improved narrow width effect and method of making thereof
A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second...
US-1,020,4999 Transistor with airgap spacer
A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a...
US-1,020,4998 Heterostructure device
A heterostructure device includes a channel layer, a barrier layer disposed on the channel layer, and a first electrode and a second electrode disposed on the...
US-1,020,4997 Thin film transistor, display substrate and display panel having the same, and fabricating method thereof
The present application discloses a thin film transistor, a display substrate and display panel having the same, and a fabricating method thereof. The thin film...
US-1,020,4996 Metal-oxide-semiconductor transistor and method of forming gate layout
A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug...
US-1,020,4995 Normally off HEMT with self aligned gate structure
A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A...
US-1,020,4994 Methods of forming a semiconductor device with a gate contact positioned above the active region
One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a...
US-1,020,4993 Power semiconductor device having a field electrode
A power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions...
US-1,020,4992 Tuned semiconductor amplifier
Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two...
US-1,020,4991 Transistor structures and fabrication methods thereof
Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially...
US-1,020,4990 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type...
US-1,020,4989 Method of fabricating semiconductor structures on dissimilar substrates
Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask...
US-1,020,4988 Graphene double-barrier resonant tunneling device
An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer...
US-1,020,4987 Semiconductor device and manufacturing method for the semiconductor device
In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column...
US-1,020,4986 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate...
US-1,020,4985 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor layer and a...
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