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Patent # Description
US-1,020,4883 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor die, an insulative layer, a conductive feature and a shield. The insulative layer surrounds the semiconductor...
US-1,020,4882 Stacked package module having an exposed heat sink surface from the packaging
A package module includes a power module, a first thermal dissipating component and a packaging plastic. The power module includes a substrate and at least one...
US-1,020,4881 Power overlay structure and reconstituted semiconductor wafer having wirebonds
A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL...
US-1,020,4880 Device and method for producing a device
A device and a method for producing a device are disclosed. In an embodiment the device includes a first component, a second component and a connecting element...
US-1,020,4879 Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric...
A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a...
US-1,020,4878 Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
US-1,020,4877 Corrosion resistant aluminum bond pad structure
A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al--Cu) layer over a dielectric layer; and depositing an ...
US-1,020,4876 Pad defined contact for wafer level package
A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined...
US-1,020,4875 Systems and methods for inhibiting backend access to integrated circuits by integrating photon and electron...
Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons,...
US-1,020,4874 Integrated circuit chip with reverse engineering prevention
An integrated circuit chip with reverse engineering prevention includes: a signal generator part configured to generate a first signal; a metal line part...
US-1,020,4873 Breakable substrate for semiconductor die
In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at...
US-1,020,4872 Power module and power conversion apparatus having a warpage suppression portion
An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the...
US-1,020,4871 Semiconductor device and semiconductor device manufacturing method
Provided is a semiconductor device including an insulating plate; a first conducting portion formed on a first surface of the insulating plate; a semiconductor...
US-1,020,4870 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip...
US-1,020,4869 Integrated circuit package including shielding between adjacent chips
An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit...
US-1,020,4867 Semiconductor metrology target and manufacturing method thereof
A metrology target of a semiconductor device is provided. The metrology target includes a substrate including first and second layers. The first layer includes...
US-1,020,4866 Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge...
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A...
US-1,020,4865 Electronic package and conductive structure thereof
An electronic package is provided, which includes: an insulator; an electronic element embedded in the insulator and having a sensing area exposed from the...
US-1,020,4864 Stretchable form of single crystal silicon for high performance electronics on rubber substrates
The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when...
US-1,020,4863 Semiconductor package structure
Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via...
US-1,020,4862 Method of manufacturing semiconductor device, and semiconductor device
A semiconductor device includes a semiconductor substrate provided with a through-hole, a device layer including a lower layer wiring, an insulating layer that...
US-1,020,4861 Structure with local contact for shorting a gate electrode to a source/drain region
The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure...
US-1,020,4860 Semiconductor device with graphene encapsulated metal and method therefor
A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least...
US-1,020,4859 Interconnect structure and fabricating method thereof
An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of...
US-1,020,4858 Semiconductor device having a multilayer wiring structure
A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of...
US-1,020,4857 Middle end-of-line strap for standard cell
A method is disclosed that includes disposing a first conductive metal segment; disposing a second conductive metal segment over an active area; disposing a...
US-1,020,4856 Interconnect structures with fully aligned vias
A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a...
US-1,020,4855 Bendable and stretchable electronic devices and methods
Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1)...
US-1,020,4854 Packaging substrate and method of fabricating the same
The packaging substrate according to the present invention is a packaging substrate including: a core substrate; an insulating layer formed on one surface or...
US-1,020,4853 Semiconductor device
A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a...
US-1,020,4852 Circuit substrate and semiconductor package structure
A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a...
US-1,020,4851 High density package interconnects
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die...
US-1,020,4850 Semiconductor package with partial plating on contact side surfaces
Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top...
US-1,020,4849 Semiconductor device
The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a...
US-1,020,4848 Semiconductor chip package having heat dissipating structure
Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured...
US-1,020,4846 Display device
A display device is disclosed. In one aspect, the display device includes a substrate including a display area configured to display an image and a peripheral...
US-1,020,4845 Semiconductor chip package having a repeating footprint pattern
A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First...
US-1,020,4844 Clip for semiconductor package
Implementations of a clip may include a die attach portion including at least one protrusion extending from the die attach portion and a lead frame alignment...
US-1,020,4843 Interconnect arrangement with stress-reducing structure and method of fabricating the same
A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a...
US-1,020,4842 Semiconductor package with a wire bond mesh
A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically...
US-1,020,4841 Temporary connection traces for wafer sort testing
A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer...
US-1,020,4840 Method for measuring gas dissociation degrees
A method for measuring gas dissociation degrees is provided. The method comprises the following steps. A reaction process with at least one reactive gas in a...
US-1,020,4839 Prevention of charging damage in full-depletion devices
Methods and systems method for checking a semiconductor device for compliance with a rule include determining whether a fully depleted semiconductor on...
US-1,020,4838 Handle substrate of composite substrate for semiconductor, and composite substrate for semiconductor
A handle substrate of a composite substrate for a semiconductor includes a base substrate comprising a polycrystalline material; and an amorphous layer provided...
US-1,020,4837 Structure and method for tensile and compressive strained silicon germanium with same germanium concentration...
A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion...
US-1,020,4836 Porous silicon relaxation medium for dislocation free CMOS devices
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer...
US-1,020,4835 Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a...
US-1,020,4834 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region...
US-1,020,4833 Array substrate and manufacturing method for the same
An array substrate and a manufacturing method. The method includes: patterning the first metal layer through a first mask to form a gate electrode and a first...
US-1,020,4832 Method of patterning intersecting structures
Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in...
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