Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,020,4831 Tape-based epitaxial lift off apparatuses and methods
Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes....
US-1,020,4830 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an...
US-1,020,4829 Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers
Methods for fabricating low-resistivity metallic interconnect structures with self-forming diffusion barrier layers are provided, as well as semiconductor...
US-1,020,4828 Enabling low resistance gates and contacts integrated with bilayer dielectrics
A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical...
US-1,020,4827 Multi-level air gap formation in dual-damascene structure
An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer...
US-1,020,4826 Method for removing damaged layer embedded in a dielectric layer
A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD...
US-1,020,4825 Semiconductor device having air gap spacers and method for fabricating the same
A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a...
US-1,020,4824 Method for producing SOI wafer
A method for producing a SOI wafer that includes implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a...
US-1,020,4823 Enhancing robustness of SOI substrate containing a buried N.sup.+ silicon layer for CMOS processing
A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided...
US-1,020,4822 Method for forming trench liner passivation
In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed...
US-1,020,4821 Semiconductor devices having isolation insulating layers and methods of manufacturing the same
The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin...
US-1,020,4820 Multi-size adaptable spin chuck system
A novel interchangeable spin chuck system is provided that allows the user to quickly change substrate sizes and spin chuck styles without any extra tools. This...
US-1,020,4819 Vapor phase growth apparatus and ring-shaped holder having a curved mounting surface with convex and concave...
A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a ring-shaped holder provided in the reaction chamber, the ring-shaped...
US-1,020,4818 Device for holding and rotating plate shaped article
A device for holding and rotating a plate shaped article comprises a group of fixed pins and a group of pivot pins arranged along the circumference of the...
US-1,020,4817 Substrate transport apparatus
A substrate transport apparatus including a frame, an upper arm rotatably mounted to the frame about a shoulder axis, a forearm rotatably mounted to the upper...
US-1,020,4816 Substrate retaining carrier, method for retaining and separating substrate and method for evaporation
A substrate retaining carrier, a method for retaining and separating the substrate, and a method for evaporation are provided. The substrate retaining carrier...
US-1,020,4815 Vacuum adsorption system, method and packaging device for mother substrate to be packaged
Vacuum adsorption system of the invention includes: vacuum adsorption platform; carrying platform, which is provided on vacuum adsorption platform and edges...
US-1,020,4814 Semiconductor package with individually molded leadframe and die coupled at solder balls
According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then...
US-1,020,4813 Wafer de-bonding device
A wafer de-bonding device comprises a stage (1) for holding a device wafer and a carrier wafer bonded together, and a tool (2) with a gas outlet (2.2) disposed...
US-1,020,4812 Method for aligning substrates before bonding
A method and corresponding device for the alignment of a first substrate comprising at least two first alignment marks with a second substrate comprising at...
US-1,020,4811 Substrate transport apparatus with active edge gripper
In accordance with one aspect of the exemplary embodiments, a substrate transport apparatus is provided comprising a drive mechanism, a movable arm assembly...
US-1,020,4810 Linear vacuum robot with Z motion and articulated arm
There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved...
US-1,020,4809 Method for thermal treatment using heat reservoir chamber
The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat...
US-1,020,4808 Micro pick and bond assembly
Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro)...
US-1,020,4807 Apparatus and method for processing wafer
An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process...
US-1,020,4806 Modular heater
A modular heater includes multiple heater modules. The heater modules can include mating features, such as a tongue and groove seal, and/or soft seal, to...
US-1,020,4805 Thin heated substrate support
The present disclosure relates to an apparatus for heating and supporting a substrate in a processing chamber. A substrate support assembly includes a heated...
US-1,020,4804 Apparatuses and methods for gas mixed liquid polishing, etching, and cleaning
In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The...
US-1,020,4803 Two step method of rapid curing a semiconductor polymer layer
A semiconductor device and method of making the semiconductor device is described. A semiconductor die can be provided. A polymer layer can be formed over the...
US-1,020,4802 Method of forming via hole, array substrate and method of forming the same and display device
The present disclosure provides a method of forming a via hole, an array substrate and a method of forming the same and a display device. The method of forming...
US-1,020,4801 Method for producing substrate for semiconductor element mounting
A process of forming, on a surface of the substrate a plurality of resist layers made of two kinds of dry film resist that differ in main peak wavelength in...
US-1,020,4800 Method for improving threshold voltage of oxide semiconductor thin film transistor
The invention provides a method for improving threshold voltage of oxide semiconductor TFT, by bending the oxide semiconductor TFT for a default number of times...
US-1,020,4799 Method for manufacturing a field-effect transistor
A method for manufacturing a field-effect transistor includes forming an active layer of an oxide semiconductor, forming a conducting film to cover the active...
US-1,020,4798 Semiconductor device, manufacturing method thereof, display device, and electronic device
The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an...
US-1,020,4797 Methods, apparatus, and system for reducing step height difference in semiconductor devices
The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a...
US-1,020,4796 Methods for selective etching of a silicon material using HF gas without nitrogen etchants
The present disclosure provides methods for etching a silicon material in a device structure in semiconductor applications. In one example, a method for etching...
US-1,020,4795 Flow distribution plate for surface fluorine reduction
A method and apparatus for processing a semiconductor substrate are described herein. A process system described herein includes a plasma source and a flow...
US-1,020,4794 Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the...
US-1,020,4793 Chemical mechanical polishing slurry, method for chemical mechanical polishing and manufacturing method of...
A chemical mechanical polishing (CMP) slurry, a method for CMP, and a manufacturing method of a semiconductor structure are provided. The CMP slurry includes a...
US-1,020,4792 Production of a thin substrate layer
A method for producing a thin substrate layer having a thickness of at most 100 .mu.m by detaching a substrate layer from the ingot by producing a tensile...
US-1,020,4791 Contact plug for high-voltage devices
A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the...
US-1,020,4790 Methods for thin film deposition
In accordance with some embodiments herein, methods for deposition of thin films are provided. In some embodiments, thin film deposition is performed in a...
US-1,020,4789 Manufacturing method of semiconductor device and semiconductor device
Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage...
US-1,020,4788 Method of forming high dielectric constant dielectric layer by atomic layer deposition
A method of forming a high dielectric constant (high-k) dielectric layer by atomic layer deposition includes the following steps. Cycles are performed one after...
US-1,020,4787 Manufacture method of polysilicon thin film and polysilicon TFT structure
The present invention provides a manufacture method of a polysilicon thin film and a polysilicon TFT structure. The manufacture method of the polysilicon thin...
US-1,020,4786 Device for connecting at least one nano-object and method of manufacturing it
Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer in...
US-1,020,4785 Substrate bonding apparatus and substrate bonding method
A substrate bonding apparatus includes a vacuum chamber, a surface activation part for activating respective bonding surfaces of a first substrate and a second...
US-1,020,4784 Methods of forming features on integrated circuit products
One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial...
US-1,020,4783 Method of forming fine island patterns of semiconductor devices
A method of forming fine island patterns of semiconductor devices includes: forming first mask pillars on a hard mask layer on a substrate; forming an upper...
US-1,020,4782 Combined anneal and selective deposition process
A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.