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Patent # Description
US-1,020,4073 Managing actions of a network device based on policy settings corresponding to a removable wireless...
A method and system for configuring a network device according to the identity of a plurality of removable wireless communications devices (RWCDs), the method...
US-1,020,4072 Method for automatically allocating addresses to similar bus users
In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the...
US-1,020,4071 Ring network system using peripheral component interconnect express and setting method thereof
A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe...
US-1,020,4070 Method, device, system and storage medium for implementing packet transmission in PCIE switching network
Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to...
US-1,020,4069 USB PHY adapter IC with and circuit VBUS present output
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus...
US-1,020,4068 Serial bus electrical termination control
Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit...
US-1,020,4067 Data transfer device of display equipment and data transfer method
A data transfer device of a display equipment and a data transfer method are provided. The data transfer device of the display equipment includes a display...
US-1,020,4066 Dynamic definition of slave address in I2C protocol
A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus....
US-1,020,4065 Methods and apparatus for a multiple master bus protocol
Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial...
US-1,020,4064 Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective...
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more...
US-1,020,4063 Local internal discovery and configuration of individually selected and jointly selected devices
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the...
US-1,020,4062 Electronic device and method for recognizing accessories
An electronic device and a method for recognizing accessories that are mounted into a connector of an electronic device are provided. The electronic device...
US-1,020,4061 Dual-system-based data storage method and terminal
A dual-system-based data storage method, comprising the steps of (S301) judging whether the data is important data when storing data in a first system; and...
US-1,020,4060 Determining memory access categories to use to assign tasks to processor cores to execute
Provided are a computer program product, system, and method for determining memory access categories to use to assign tasks to processor cores to execute. A...
US-1,020,4059 Memory optimization by phase-dependent data residency
Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time...
US-1,020,4058 GPU shared virtual memory working set management
A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a...
US-1,020,4057 Memory emulation mechanism
In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing...
US-1,020,4056 Dynamic cache enlarging by counting evictions
A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full...
US-1,020,4055 System and methods for expandably wide processor instructions
Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The...
US-1,020,4054 Media cache cleaning
Implementations disclosed herein provide a method comprising detecting a power supply status, determining a media cache cleaning scheme based on the detected...
US-1,020,4053 Modeling processor shared memory using a cacheability status
A method may include assigning a cacheability status to a page. The page may be in a memory of a host computer communicatively connected to a processor core on...
US-1,020,4052 Directory maintenance method and apparatus
A directory maintenance method and apparatus are provided. The method includes sending, by a main memory according to a correspondence between a cache line in a...
US-1,020,4051 Technique to share information among different cache coherency domains
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches...
US-1,020,4050 Memory-side caching for shared memory objects
Methods and systems for memory-side shared caching include determining whether a requested memory access is directed to shared portion of memory by referencing...
US-1,020,4049 Value of forward state by increasing local caching agent forwarding
Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the...
US-1,020,4048 Replicating a primary application cache within a secondary application cache
Replicating a primary application cache that serves a primary application on one network node into a secondary application cache that serves a secondary...
US-1,020,4047 Memory controller for multi-level system memory with coherency unit
An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a...
US-1,020,4046 High-speed and memory-efficient flow cache for network flow processors
The flow cache of a network flow processor (NFP) stores flow lookup information in cache lines. Some cache lines are stored in external bulk memory and others...
US-1,020,4045 Data file handling in a volatile memory
A mechanism is provided for destaging one or more data files in a volatile memory using a set of heat registers associated with each data file. Responsive to...
US-1,020,4044 Memory management process using data sheet
Provided are a device and method of managing data stored in memory. The device may include a buffer for storing data blocks including a head data block, a tail...
US-1,020,4043 Memory controller, method of controlling nonvolatile memory and memory system
According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit generates first compressed data...
US-1,020,4042 Memory system having persistent garbage collection
Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased,...
US-1,020,4041 Relocating data in a memory device
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory...
US-1,020,4040 High speed flash controllers
A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB...
US-1,020,4039 Host controlled hybrid storage device
A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge...
US-1,020,4038 System and method of embedding messages into trace data
In one or more embodiments, one or more methods, processes and/or systems may receive multiple characters (e.g., a string), determine multiple offsets...
US-1,020,4037 Memory device, memory controller and operation method thereof
An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data...
US-1,020,4036 System and method for altering application functionality
Disclosed are systems and methods for altering a functionality of an application installed in a computer. In one aspect, an exemplary method comprises, by a...
US-1,020,4035 Systems, methods and devices for AI-driven automatic test generation
A test script is generated in an automated fashion based on a master key file (and optionally, additionally based on user logs) in order to test a software...
US-1,020,4034 System and method for testing software applications in a software defined network
A system, method and computer-readable medium for testing a service-based application identifies a set of use cases for the service-based application. Each use...
US-1,020,4033 Method and system for semantic test suite reduction
Methods, non-transitory computer readable media, test management computing devices that obtain test scripts associated with a test suite for testing an...
US-1,020,4032 Generating test data from samples using natural language processing and structure-based pattern determination
A method may include receiving a plurality of samples that include textual content. The method may include extracting unit values, corresponding to structural...
US-1,020,4031 Methods and system to create applications and distribute applications to a remote device
A remotely accessible integrated development environment, and a sub-system for deploying applications to a remote device is disclosed. The sub-system may...
US-1,020,4030 Debug session tree recorder with generic playback
Specific example debugging sessions are used to generate a generic decision tree (flow diagram) for use in future debugging sessions. Debug metadata is recorded...
US-1,020,4029 Stack pattern breakpoint in COBOL
Examples of techniques for setting a stack pattern breakpoint for a COBOL program are disclosed. In one example implementation according to aspects of the...
US-1,020,4028 Rule spaces and architecture root detection
Errors in software may be detected via the use of design rule spaces and architecture root detection. Design rule spaces may reveal multiple overlapping modular...
US-1,020,4027 Log information collection system and log information collection method
A log information collection system includes a first storage device, to-be-monitored devices each including a second memory, a monitor device including a third...
US-1,020,4026 Realtime data stream cluster summarization and labeling system
A method is provided for automatically discovering topics in electronic posts, such as social media posts. The method includes receiving a corpus that includes...
US-1,020,4025 Mechanism to provide back-to-back testing of memory controller operation
Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test...
US-1,020,4024 Sent error generator
A test generator includes a computer programmed to receive at least one input instruction including a message to be transmitted by the test generator and an...
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